panfrost: Fix linear depth textures
As pointed out by Boris, what we were calling PAN_LINEAR depth textures was in fact u-interleaved tiled (!), but we never noticed since we flipped the flag used for sampling, leading to all sorts of fun bugs when attempting to directly acess depth textures from the CPU. Which begs the question -- if what we called LINEAR was tiled, how do we actually render linear depth textures? It turns out the flags for AFBC form a mali_block_format 2-bit code just like their render-target counterparts, so we can render to any of the above. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reported-by: Boris Brezillon <boris.brezillon@collabora.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393>
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Marge Bot

parent
7c16a1ae4e
commit
6bd9c4dc57
@@ -504,17 +504,13 @@ panfrost_upload_sampler_descriptors(struct panfrost_context *ctx)
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static enum mali_texture_layout
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panfrost_layout_for_texture(struct panfrost_resource *rsrc)
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{
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/* TODO: other linear depth textures */
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bool is_depth = rsrc->base.format == PIPE_FORMAT_Z32_UNORM;
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switch (rsrc->layout) {
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case PAN_AFBC:
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return MALI_TEXTURE_AFBC;
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case PAN_TILED:
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assert(!is_depth);
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return MALI_TEXTURE_TILED;
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case PAN_LINEAR:
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return is_depth ? MALI_TEXTURE_TILED : MALI_TEXTURE_LINEAR;
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return MALI_TEXTURE_LINEAR;
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default:
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unreachable("Invalid texture layout");
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}
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@@ -249,12 +249,9 @@ panfrost_mfbd_set_zsbuf(
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fb->mfbd_flags |= MALI_MFBD_EXTRA;
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fbx->flags =
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MALI_EXTRA_PRESENT |
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MALI_EXTRA_AFBC |
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MALI_EXTRA_AFBC_ZS |
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MALI_EXTRA_ZS |
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0x1; /* unknown */
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fbx->flags_hi |= MALI_EXTRA_PRESENT;
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fbx->flags_lo |= MALI_EXTRA_ZS | 0x1; /* unknown */
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fbx->zs_block = MALI_BLOCK_AFBC;
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fbx->ds_afbc.depth_stencil = base + header_size;
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fbx->ds_afbc.depth_stencil_afbc_metadata = base;
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@@ -262,27 +259,36 @@ panfrost_mfbd_set_zsbuf(
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fbx->ds_afbc.zero1 = 0x10009;
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fbx->ds_afbc.padding = 0x1000;
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} else if (rsrc->layout == PAN_LINEAR) {
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} else if (rsrc->layout == PAN_LINEAR || rsrc->layout == PAN_TILED) {
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/* TODO: Z32F(S8) support, which is always linear */
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int stride = rsrc->slices[level].stride;
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fb->mfbd_flags |= MALI_MFBD_EXTRA;
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fbx->flags |= MALI_EXTRA_PRESENT | MALI_EXTRA_ZS;
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fbx->flags_hi |= MALI_EXTRA_PRESENT;
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fbx->flags_lo |= MALI_EXTRA_ZS;
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fbx->ds_linear.depth = base;
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fbx->ds_linear.depth_stride = stride;
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if (rsrc->layout == PAN_LINEAR) {
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fbx->zs_block = MALI_BLOCK_LINEAR;
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fbx->ds_linear.depth_stride = stride / 16;
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} else {
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fbx->zs_block = MALI_BLOCK_TILED;
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fbx->ds_linear.depth_stride = stride;
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}
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if (panfrost_is_z24s8_variant(surf->format)) {
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fbx->flags |= 0x1;
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fbx->flags_lo |= 0x1;
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} else if (surf->format == PIPE_FORMAT_Z32_UNORM) {
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/* default flags (0 in bottom place) */
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} else if (surf->format == PIPE_FORMAT_Z32_FLOAT) {
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fbx->flags |= 0xA;
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fbx->flags_lo |= 0xA;
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fb->mfbd_flags ^= 0x100;
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fb->mfbd_flags |= 0x200;
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} else if (surf->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
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fbx->flags |= 0x1000A;
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fbx->flags_hi |= 0x400;
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fbx->flags_lo |= 0xA;
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fb->mfbd_flags ^= 0x100;
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fb->mfbd_flags |= 0x201;
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@@ -484,7 +490,7 @@ panfrost_mfbd_fragment(struct panfrost_batch *batch, bool has_draws)
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struct panfrost_slice *slice = &rsrc->slices[level];
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fb.mfbd_flags |= MALI_MFBD_EXTRA;
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fbx.flags |= MALI_EXTRA_PRESENT;
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fbx.flags_lo |= MALI_EXTRA_PRESENT;
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fbx.checksum_stride = slice->checksum_stride;
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fbx.checksum = bo->gpu + slice->checksum_offset;
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}
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@@ -47,6 +47,7 @@
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#include "pan_resource.h"
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#include "pan_util.h"
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#include "pan_tiling.h"
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#include "panfrost-quirks.h"
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void
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panfrost_resource_reset_damage(struct panfrost_resource *pres)
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@@ -395,6 +396,7 @@ panfrost_resource_create_bo(struct panfrost_screen *screen, struct panfrost_reso
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* (a combination of) one of the following */
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const unsigned valid_binding =
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PIPE_BIND_DEPTH_STENCIL |
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PIPE_BIND_RENDER_TARGET |
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PIPE_BIND_BLENDABLE |
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PIPE_BIND_SAMPLER_VIEW |
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@@ -402,6 +404,7 @@ panfrost_resource_create_bo(struct panfrost_screen *screen, struct panfrost_reso
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bool is_2d = (res->target == PIPE_TEXTURE_2D);
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bool should_tile = (res->usage != PIPE_USAGE_STREAM);
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bool must_tile = (res->bind & PIPE_BIND_DEPTH_STENCIL) && (screen->quirks & MIDGARD_SFBD);
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bool can_tile = is_2d && ((res->bind & ~valid_binding) == 0);
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/* FBOs we would like to checksum, if at all possible */
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@@ -411,7 +414,8 @@ panfrost_resource_create_bo(struct panfrost_screen *screen, struct panfrost_reso
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pres->checksummed = can_checksum && should_checksum;
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/* Set the layout appropriately */
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pres->layout = (can_tile && should_tile) ? PAN_TILED : PAN_LINEAR;
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assert(!(must_tile && !can_tile)); /* must_tile => can_tile */
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pres->layout = ((can_tile && should_tile) || must_tile) ? PAN_TILED : PAN_LINEAR;
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size_t bo_size;
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@@ -163,7 +163,7 @@ panfrost_sfbd_set_zsbuf(
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unsigned level = surf->u.tex.level;
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assert(surf->u.tex.first_layer == 0);
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if (rsrc->layout != PAN_LINEAR)
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if (rsrc->layout != PAN_TILED)
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unreachable("Invalid render layout.");
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fb->depth_buffer = rsrc->bo->gpu + rsrc->slices[level].offset;
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@@ -1597,11 +1597,10 @@ struct bifrost_render_target {
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* - TODO: Anything else?
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*/
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/* Flags field: note, these are guesses */
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/* flags_hi */
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#define MALI_EXTRA_PRESENT (0x10)
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#define MALI_EXTRA_PRESENT (0x400)
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#define MALI_EXTRA_AFBC (0x20)
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#define MALI_EXTRA_AFBC_ZS (0x10)
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/* flags_lo */
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#define MALI_EXTRA_ZS (0x4)
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struct bifrost_fb_extra {
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@@ -1609,7 +1608,9 @@ struct bifrost_fb_extra {
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/* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
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u32 checksum_stride;
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u32 flags;
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unsigned flags_lo : 4;
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enum mali_block_format zs_block : 2;
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unsigned flags_hi : 26;
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union {
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/* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
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@@ -247,9 +247,14 @@ static const struct pandecode_flag_info mfbd_fmt_flag_info[] = {
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#undef FLAG_INFO
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#define FLAG_INFO(flag) { MALI_EXTRA_##flag, "MALI_EXTRA_" #flag }
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static const struct pandecode_flag_info mfbd_extra_flag_info[] = {
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static const struct pandecode_flag_info mfbd_extra_flag_hi_info[] = {
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FLAG_INFO(PRESENT),
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FLAG_INFO(AFBC),
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{}
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};
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#undef FLAG_INFO
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#define FLAG_INFO(flag) { MALI_EXTRA_##flag, "MALI_EXTRA_" #flag }
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static const struct pandecode_flag_info mfbd_extra_flag_lo_info[] = {
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FLAG_INFO(ZS),
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{}
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};
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@@ -1128,11 +1133,17 @@ pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment)
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if (fbx->checksum_stride)
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pandecode_prop("checksum_stride = %d", fbx->checksum_stride);
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pandecode_log(".flags = ");
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pandecode_log_decoded_flags(mfbd_extra_flag_info, fbx->flags);
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pandecode_log(".flags_hi = ");
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pandecode_log_decoded_flags(mfbd_extra_flag_hi_info, fbx->flags_lo);
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pandecode_log_cont(",\n");
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if (fbx->flags & MALI_EXTRA_AFBC_ZS) {
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pandecode_log(".flags_lo = ");
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pandecode_log_decoded_flags(mfbd_extra_flag_lo_info, fbx->flags_lo);
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pandecode_log_cont(",\n");
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pandecode_prop("zs_block = %s\n", pandecode_block_format(fbx->zs_block));
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if (fbx->zs_block == MALI_BLOCK_AFBC) {
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pandecode_log(".ds_afbc = {\n");
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pandecode_indent++;
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@@ -1159,12 +1170,16 @@ pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment)
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MEMORY_PROP_DIR(fbx->ds_linear, depth);
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pandecode_prop("depth_stride = %d",
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fbx->ds_linear.depth_stride);
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} else if (fbx->ds_linear.depth_stride) {
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pandecode_msg("XXX: depth stride zero tripped %d\n", fbx->ds_linear.depth_stride);
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}
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if (fbx->ds_linear.stencil) {
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MEMORY_PROP_DIR(fbx->ds_linear, stencil);
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pandecode_prop("stencil_stride = %d",
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fbx->ds_linear.stencil_stride);
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} else if (fbx->ds_linear.stencil_stride) {
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pandecode_msg("XXX: stencil stride zero tripped %d\n", fbx->ds_linear.stencil_stride);
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}
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if (fbx->ds_linear.depth_stride_zero ||
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@@ -1933,7 +1948,7 @@ pandecode_texture(mali_ptr u,
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if (f.layout == MALI_TEXTURE_AFBC)
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pandecode_log_cont("afbc");
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else if (f.layout == MALI_TEXTURE_TILED)
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pandecode_log_cont(is_zs ? "linear" : "tiled");
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pandecode_log_cont("tiled");
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else if (f.layout == MALI_TEXTURE_LINEAR)
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pandecode_log_cont("linear");
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else
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