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intel/brw: Remove duplicated functions between fs_reg/brw_reg

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Update the brw_reg ones and use them.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29791>
This commit is contained in:
Caio Oliveira
2024-06-18 22:19:57 -07:00
committed by Marge Bot
parent d00329e821
commit 6b2405e1f5
3 changed files with 35 additions and 81 deletions
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72
src/intel/compiler/brw_ir_fs.h
View File

@@ -34,46 +34,6 @@ public:
fs_reg(struct ::brw_reg reg) : brw_reg(reg) {}
};
static inline fs_reg
negate(fs_reg reg)
{
assert(reg.file != IMM);
reg.negate = !reg.negate;
return reg;
}
static inline fs_reg
retype(fs_reg reg, enum brw_reg_type type)
{
reg.type = type;
return reg;
}
static inline fs_reg
byte_offset(fs_reg reg, unsigned delta)
{
switch (reg.file) {
case BAD_FILE:
break;
case VGRF:
case ATTR:
case UNIFORM:
reg.offset += delta;
break;
case ARF:
case FIXED_GRF: {
const unsigned suboffset = reg.subnr + delta;
reg.nr += suboffset / REG_SIZE;
reg.subnr = suboffset % REG_SIZE;
break;
}
case IMM:
default:
assert(delta == 0);
}
return reg;
}
static inline fs_reg
horiz_offset(const fs_reg &reg, unsigned delta)
{
@@ -262,38 +222,6 @@ quarter(const fs_reg &reg, unsigned idx)
return horiz_offset(reg, 8 * idx);
}
/**
* Reinterpret each channel of register \p reg as a vector of values of the
* given smaller type and take the i-th subcomponent from each.
*/
static inline fs_reg
subscript(fs_reg reg, brw_reg_type type, unsigned i)
{
assert((i + 1) * brw_type_size_bytes(type) <= brw_type_size_bytes(reg.type));
if (reg.file == ARF || reg.file == FIXED_GRF) {
/* The stride is encoded inconsistently for fixed GRF and ARF registers
* as the log2 of the actual vertical and horizontal strides.
*/
const int delta = util_logbase2(brw_type_size_bytes(reg.type)) -
util_logbase2(brw_type_size_bytes(type));
reg.hstride += (reg.hstride ? delta : 0);
reg.vstride += (reg.vstride ? delta : 0);
} else if (reg.file == IMM) {
unsigned bit_size = brw_type_size_bits(type);
reg.u64 >>= i * bit_size;
reg.u64 &= BITFIELD64_MASK(bit_size);
if (bit_size <= 16)
reg.u64 |= reg.u64 << 16;
return retype(reg, type);
} else {
reg.stride *= brw_type_size_bytes(reg.type) / brw_type_size_bytes(type);
}
return byte_offset(retype(reg, type), i * brw_type_size_bytes(type));
}
static inline fs_reg
horiz_stride(fs_reg reg, unsigned s)
{

4
src/intel/compiler/brw_lower_logical_sends.cpp
View File

@@ -995,12 +995,12 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst,
sources[length] = retype(sources[length], payload_unsigned_type);
bld.MOV(sources[length++],
mcs.file == IMM ? mcs :
subscript(tmp, payload_unsigned_type, 0));
fs_reg(subscript(tmp, payload_unsigned_type, 0)));
sources[length] = retype(sources[length], payload_unsigned_type);
bld.MOV(sources[length++],
mcs.file == IMM ? mcs :
subscript(tmp, payload_unsigned_type, 1));
fs_reg(subscript(tmp, payload_unsigned_type, 1)));
} else {
sources[length] = retype(sources[length], payload_unsigned_type);
bld.MOV(sources[length++],

40
src/intel/compiler/brw_reg.h
View File

@@ -546,9 +546,25 @@ offset(struct brw_reg reg, unsigned delta)
static inline struct brw_reg
byte_offset(struct brw_reg reg, unsigned bytes)
{
unsigned newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
reg.nr = newoffset / REG_SIZE;
reg.subnr = newoffset % REG_SIZE;
switch (reg.file) {
case BAD_FILE:
break;
case VGRF:
case ATTR:
case UNIFORM:
reg.offset += bytes;
break;
case ARF:
case FIXED_GRF: {
const unsigned suboffset = reg.subnr + bytes;
reg.nr += suboffset / REG_SIZE;
reg.subnr = suboffset % REG_SIZE;
break;
}
case IMM:
default:
assert(bytes == 0);
}
return reg;
}
@@ -1063,19 +1079,29 @@ spread(struct brw_reg reg, unsigned s)
static inline struct brw_reg
subscript(struct brw_reg reg, enum brw_reg_type type, unsigned i)
{
unsigned scale = brw_type_size_bytes(reg.type) / brw_type_size_bytes(type);
assert(scale >= 1 && i < scale);
assert((i + 1) * brw_type_size_bytes(type) <= brw_type_size_bytes(reg.type));
if (reg.file == IMM) {
if (reg.file == ARF || reg.file == FIXED_GRF) {
/* The stride is encoded inconsistently for fixed GRF and ARF registers
* as the log2 of the actual vertical and horizontal strides.
*/
const int delta = util_logbase2(brw_type_size_bytes(reg.type)) -
util_logbase2(brw_type_size_bytes(type));
reg.hstride += (reg.hstride ? delta : 0);
reg.vstride += (reg.vstride ? delta : 0);
} else if (reg.file == IMM) {
unsigned bit_size = brw_type_size_bits(type);
reg.u64 >>= i * bit_size;
reg.u64 &= BITFIELD64_MASK(bit_size);
if (bit_size <= 16)
reg.u64 |= reg.u64 << 16;
return retype(reg, type);
} else {
reg.stride *= brw_type_size_bytes(reg.type) / brw_type_size_bytes(type);
}
return suboffset(retype(spread(reg, scale), type), i);
return byte_offset(retype(reg, type), i * brw_type_size_bytes(type));
}
static inline struct brw_reg