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anv: Program and emit STATE_COMPUTE_MODE

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Don't rely on the HW to set values correctly so just emit
STATE_COMPUTE_MODE with default values set to zero.

Also, this change includes workaround changes:-
   - 14015808183 (Parent HSD 14015782607)  - Need to emit pipe control
     with HDC flush and untyped cache flush set to 1 when CCS has
     non-pipelined state update with STATE_COMPUTE_MODE.
   - 14014427904 (Parent HSD 22013045878) - We need additional
     invalidate/flush when emitting non-pipelined state commands with
     multiple CCS enabled.

v2: (Tapani)
- Use lineage HSD numbers for check
- Don't use poisoned WA directly
- Use intel_needs_workaround helper

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24508>
This commit is contained in:
Sagar Ghuge
2023-08-04 14:09:40 -07:00
committed by Marge Bot
parent f0d5c7848a
commit 6a89507be8
1 changed files with 20 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
src/intel/vulkan/genX_init_state.c
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@@ -567,6 +567,7 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
#endif
#if GFX_VERx10 >= 125
anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), zero);
anv_batch_emit(&batch, GENX(3DSTATE_MESH_CONTROL), zero);
anv_batch_emit(&batch, GENX(3DSTATE_TASK_CONTROL), zero);
genX(batch_emit_pipe_control_write)(&batch, device->info, NoWrite,
@@ -622,14 +623,26 @@ init_compute_queue_state(struct anv_queue *queue)
assert(!queue->device->info->has_aux_map);
#endif
#if GFX_VERx10 == 125
/* Wa_14014427904 - We need additional invalidate/flush when
/* Wa_14015782607 - Issue pipe control with HDC_flush and
* untyped cache flush set to 1 when CCS has NP state update with
* STATE_COMPUTE_MODE.
*/
if (intel_needs_workaround(devinfo, 14015782607) &&
queue->family->engine_class == INTEL_ENGINE_CLASS_COMPUTE) {
genX(batch_emit_pipe_control)(&batch, devinfo,
ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT |
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT);
}
#if GFX_VERx10 >= 125
/* Wa_14014427904/22013045878 - We need additional invalidate/flush when
* emitting NP state commands with ATS-M in compute mode.
*/
if (intel_device_info_is_atsm(queue->device->info) &&
if (intel_device_info_is_atsm(devinfo) &&
queue->family->engine_class == INTEL_ENGINE_CLASS_COMPUTE) {
genX(batch_emit_pipe_control)
(&batch, queue->device->info,
(&batch, devinfo,
ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_STATE_CACHE_INVALIDATE_BIT |
ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
@@ -637,7 +650,9 @@ init_compute_queue_state(struct anv_queue *queue)
ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT |
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT);
}
}
anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), zero);
#endif
init_common_queue_state(queue, &batch);