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intel: Rename GEN_{ALL, LT, ..} macros to GFX_{ALL, LT, ..}

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Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_\(ALL\|GE\|GT\|LT\|LE\)\([^[:alnum:]]\)/GFX_\1\2/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
This commit is contained in:
Anuj Phogat
2021-03-19 17:27:26 -07:00
committed by Marge Bot
parent ddb04b31fd
commit 69c3578c8b
3 changed files with 110 additions and 110 deletions
Download Patch File Download Diff File Expand all files Collapse all files

194
src/intel/compiler/brw_eu.cpp
View File

@@ -590,111 +590,111 @@ brw_disassemble(const struct gen_device_info *devinfo,
static const struct opcode_desc opcode_descs[] = { static const struct opcode_desc opcode_descs[] = {
/* IR, HW, name, nsrc, ndst, gens */ /* IR, HW, name, nsrc, ndst, gens */
{ BRW_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GEN_ALL }, { BRW_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GFX_ALL },
{ BRW_OPCODE_SYNC, 1, "sync", 1, 0, GEN_GE(GFX12) }, { BRW_OPCODE_SYNC, 1, "sync", 1, 0, GFX_GE(GFX12) },
{ BRW_OPCODE_MOV, 1, "mov", 1, 1, GEN_LT(GFX12) }, { BRW_OPCODE_MOV, 1, "mov", 1, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_MOV, 97, "mov", 1, 1, GEN_GE(GFX12) }, { BRW_OPCODE_MOV, 97, "mov", 1, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_SEL, 2, "sel", 2, 1, GEN_LT(GFX12) }, { BRW_OPCODE_SEL, 2, "sel", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SEL, 98, "sel", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_SEL, 98, "sel", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_MOVI, 3, "movi", 2, 1, GEN_GE(GFX45) & GEN_LT(GFX12) }, { BRW_OPCODE_MOVI, 3, "movi", 2, 1, GFX_GE(GFX45) & GFX_LT(GFX12) },
{ BRW_OPCODE_MOVI, 99, "movi", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_MOVI, 99, "movi", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_NOT, 4, "not", 1, 1, GEN_LT(GFX12) }, { BRW_OPCODE_NOT, 4, "not", 1, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_NOT, 100, "not", 1, 1, GEN_GE(GFX12) }, { BRW_OPCODE_NOT, 100, "not", 1, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_AND, 5, "and", 2, 1, GEN_LT(GFX12) }, { BRW_OPCODE_AND, 5, "and", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_AND, 101, "and", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_AND, 101, "and", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_OR, 6, "or", 2, 1, GEN_LT(GFX12) }, { BRW_OPCODE_OR, 6, "or", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_OR, 102, "or", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_OR, 102, "or", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_XOR, 7, "xor", 2, 1, GEN_LT(GFX12) }, { BRW_OPCODE_XOR, 7, "xor", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_XOR, 103, "xor", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_XOR, 103, "xor", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_SHR, 8, "shr", 2, 1, GEN_LT(GFX12) }, { BRW_OPCODE_SHR, 8, "shr", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SHR, 104, "shr", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_SHR, 104, "shr", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_SHL, 9, "shl", 2, 1, GEN_LT(GFX12) }, { BRW_OPCODE_SHL, 9, "shl", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SHL, 105, "shl", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_SHL, 105, "shl", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_DIM, 10, "dim", 1, 1, GFX75 }, { BRW_OPCODE_DIM, 10, "dim", 1, 1, GFX75 },
{ BRW_OPCODE_SMOV, 10, "smov", 0, 0, GEN_GE(GFX8) & GEN_LT(GFX12) }, { BRW_OPCODE_SMOV, 10, "smov", 0, 0, GFX_GE(GFX8) & GFX_LT(GFX12) },
{ BRW_OPCODE_SMOV, 106, "smov", 0, 0, GEN_GE(GFX12) }, { BRW_OPCODE_SMOV, 106, "smov", 0, 0, GFX_GE(GFX12) },
{ BRW_OPCODE_ASR, 12, "asr", 2, 1, GEN_LT(GFX12) }, { BRW_OPCODE_ASR, 12, "asr", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_ASR, 108, "asr", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_ASR, 108, "asr", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_ROR, 14, "ror", 2, 1, GFX11 }, { BRW_OPCODE_ROR, 14, "ror", 2, 1, GFX11 },
{ BRW_OPCODE_ROR, 110, "ror", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_ROR, 110, "ror", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_ROL, 15, "rol", 2, 1, GFX11 }, { BRW_OPCODE_ROL, 15, "rol", 2, 1, GFX11 },
{ BRW_OPCODE_ROL, 111, "rol", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_ROL, 111, "rol", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_CMP, 16, "cmp", 2, 1, GEN_LT(GFX12) }, { BRW_OPCODE_CMP, 16, "cmp", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_CMP, 112, "cmp", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_CMP, 112, "cmp", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_CMPN, 17, "cmpn", 2, 1, GEN_LT(GFX12) }, { BRW_OPCODE_CMPN, 17, "cmpn", 2, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_CMPN, 113, "cmpn", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_CMPN, 113, "cmpn", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_CSEL, 18, "csel", 3, 1, GEN_GE(GFX8) & GEN_LT(GFX12) }, { BRW_OPCODE_CSEL, 18, "csel", 3, 1, GFX_GE(GFX8) & GFX_LT(GFX12) },
{ BRW_OPCODE_CSEL, 114, "csel", 3, 1, GEN_GE(GFX12) }, { BRW_OPCODE_CSEL, 114, "csel", 3, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 }, { BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 },
{ BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 }, { BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 },
{ BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GEN_GE(GFX7) & GEN_LT(GFX12) }, { BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ BRW_OPCODE_BFREV, 119, "bfrev", 1, 1, GEN_GE(GFX12) }, { BRW_OPCODE_BFREV, 119, "bfrev", 1, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_BFE, 24, "bfe", 3, 1, GEN_GE(GFX7) & GEN_LT(GFX12) }, { BRW_OPCODE_BFE, 24, "bfe", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ BRW_OPCODE_BFE, 120, "bfe", 3, 1, GEN_GE(GFX12) }, { BRW_OPCODE_BFE, 120, "bfe", 3, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_BFI1, 25, "bfi1", 2, 1, GEN_GE(GFX7) & GEN_LT(GFX12) }, { BRW_OPCODE_BFI1, 25, "bfi1", 2, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ BRW_OPCODE_BFI1, 121, "bfi1", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_BFI1, 121, "bfi1", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_BFI2, 26, "bfi2", 3, 1, GEN_GE(GFX7) & GEN_LT(GFX12) }, { BRW_OPCODE_BFI2, 26, "bfi2", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ BRW_OPCODE_BFI2, 122, "bfi2", 3, 1, GEN_GE(GFX12) }, { BRW_OPCODE_BFI2, 122, "bfi2", 3, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_JMPI, 32, "jmpi", 0, 0, GEN_ALL }, { BRW_OPCODE_JMPI, 32, "jmpi", 0, 0, GFX_ALL },
{ BRW_OPCODE_BRD, 33, "brd", 0, 0, GEN_GE(GFX7) }, { BRW_OPCODE_BRD, 33, "brd", 0, 0, GFX_GE(GFX7) },
{ BRW_OPCODE_IF, 34, "if", 0, 0, GEN_ALL }, { BRW_OPCODE_IF, 34, "if", 0, 0, GFX_ALL },
{ BRW_OPCODE_IFF, 35, "iff", 0, 0, GEN_LE(GFX5) }, { BRW_OPCODE_IFF, 35, "iff", 0, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_BRC, 35, "brc", 0, 0, GEN_GE(GFX7) }, { BRW_OPCODE_BRC, 35, "brc", 0, 0, GFX_GE(GFX7) },
{ BRW_OPCODE_ELSE, 36, "else", 0, 0, GEN_ALL }, { BRW_OPCODE_ELSE, 36, "else", 0, 0, GFX_ALL },
{ BRW_OPCODE_ENDIF, 37, "endif", 0, 0, GEN_ALL }, { BRW_OPCODE_ENDIF, 37, "endif", 0, 0, GFX_ALL },
{ BRW_OPCODE_DO, 38, "do", 0, 0, GEN_LE(GFX5) }, { BRW_OPCODE_DO, 38, "do", 0, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_CASE, 38, "case", 0, 0, GFX6 }, { BRW_OPCODE_CASE, 38, "case", 0, 0, GFX6 },
{ BRW_OPCODE_WHILE, 39, "while", 0, 0, GEN_ALL }, { BRW_OPCODE_WHILE, 39, "while", 0, 0, GFX_ALL },
{ BRW_OPCODE_BREAK, 40, "break", 0, 0, GEN_ALL }, { BRW_OPCODE_BREAK, 40, "break", 0, 0, GFX_ALL },
{ BRW_OPCODE_CONTINUE, 41, "cont", 0, 0, GEN_ALL }, { BRW_OPCODE_CONTINUE, 41, "cont", 0, 0, GFX_ALL },
{ BRW_OPCODE_HALT, 42, "halt", 0, 0, GEN_ALL }, { BRW_OPCODE_HALT, 42, "halt", 0, 0, GFX_ALL },
{ BRW_OPCODE_CALLA, 43, "calla", 0, 0, GEN_GE(GFX75) }, { BRW_OPCODE_CALLA, 43, "calla", 0, 0, GFX_GE(GFX75) },
{ BRW_OPCODE_MSAVE, 44, "msave", 0, 0, GEN_LE(GFX5) }, { BRW_OPCODE_MSAVE, 44, "msave", 0, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_CALL, 44, "call", 0, 0, GEN_GE(GFX6) }, { BRW_OPCODE_CALL, 44, "call", 0, 0, GFX_GE(GFX6) },
{ BRW_OPCODE_MREST, 45, "mrest", 0, 0, GEN_LE(GFX5) }, { BRW_OPCODE_MREST, 45, "mrest", 0, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_RET, 45, "ret", 0, 0, GEN_GE(GFX6) }, { BRW_OPCODE_RET, 45, "ret", 0, 0, GFX_GE(GFX6) },
{ BRW_OPCODE_PUSH, 46, "push", 0, 0, GEN_LE(GFX5) }, { BRW_OPCODE_PUSH, 46, "push", 0, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_FORK, 46, "fork", 0, 0, GFX6 }, { BRW_OPCODE_FORK, 46, "fork", 0, 0, GFX6 },
{ BRW_OPCODE_GOTO, 46, "goto", 0, 0, GEN_GE(GFX8) }, { BRW_OPCODE_GOTO, 46, "goto", 0, 0, GFX_GE(GFX8) },
{ BRW_OPCODE_POP, 47, "pop", 2, 0, GEN_LE(GFX5) }, { BRW_OPCODE_POP, 47, "pop", 2, 0, GFX_LE(GFX5) },
{ BRW_OPCODE_WAIT, 48, "wait", 0, 1, GEN_LT(GFX12) }, { BRW_OPCODE_WAIT, 48, "wait", 0, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SEND, 49, "send", 1, 1, GEN_LT(GFX12) }, { BRW_OPCODE_SEND, 49, "send", 1, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SENDC, 50, "sendc", 1, 1, GEN_LT(GFX12) }, { BRW_OPCODE_SENDC, 50, "sendc", 1, 1, GFX_LT(GFX12) },
{ BRW_OPCODE_SEND, 49, "send", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_SEND, 49, "send", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_SENDC, 50, "sendc", 2, 1, GEN_GE(GFX12) }, { BRW_OPCODE_SENDC, 50, "sendc", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_SENDS, 51, "sends", 2, 1, GEN_GE(GFX9) & GEN_LT(GFX12) }, { BRW_OPCODE_SENDS, 51, "sends", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) },
{ BRW_OPCODE_SENDSC, 52, "sendsc", 2, 1, GEN_GE(GFX9) & GEN_LT(GFX12) }, { BRW_OPCODE_SENDSC, 52, "sendsc", 2, 1, GFX_GE(GFX9) & GFX_LT(GFX12) },
{ BRW_OPCODE_MATH, 56, "math", 2, 1, GEN_GE(GFX6) }, { BRW_OPCODE_MATH, 56, "math", 2, 1, GFX_GE(GFX6) },
{ BRW_OPCODE_ADD, 64, "add", 2, 1, GEN_ALL }, { BRW_OPCODE_ADD, 64, "add", 2, 1, GFX_ALL },
{ BRW_OPCODE_MUL, 65, "mul", 2, 1, GEN_ALL }, { BRW_OPCODE_MUL, 65, "mul", 2, 1, GFX_ALL },
{ BRW_OPCODE_AVG, 66, "avg", 2, 1, GEN_ALL }, { BRW_OPCODE_AVG, 66, "avg", 2, 1, GFX_ALL },
{ BRW_OPCODE_FRC, 67, "frc", 1, 1, GEN_ALL }, { BRW_OPCODE_FRC, 67, "frc", 1, 1, GFX_ALL },
{ BRW_OPCODE_RNDU, 68, "rndu", 1, 1, GEN_ALL }, { BRW_OPCODE_RNDU, 68, "rndu", 1, 1, GFX_ALL },
{ BRW_OPCODE_RNDD, 69, "rndd", 1, 1, GEN_ALL }, { BRW_OPCODE_RNDD, 69, "rndd", 1, 1, GFX_ALL },
{ BRW_OPCODE_RNDE, 70, "rnde", 1, 1, GEN_ALL }, { BRW_OPCODE_RNDE, 70, "rnde", 1, 1, GFX_ALL },
{ BRW_OPCODE_RNDZ, 71, "rndz", 1, 1, GEN_ALL }, { BRW_OPCODE_RNDZ, 71, "rndz", 1, 1, GFX_ALL },
{ BRW_OPCODE_MAC, 72, "mac", 2, 1, GEN_ALL }, { BRW_OPCODE_MAC, 72, "mac", 2, 1, GFX_ALL },
{ BRW_OPCODE_MACH, 73, "mach", 2, 1, GEN_ALL }, { BRW_OPCODE_MACH, 73, "mach", 2, 1, GFX_ALL },
{ BRW_OPCODE_LZD, 74, "lzd", 1, 1, GEN_ALL }, { BRW_OPCODE_LZD, 74, "lzd", 1, 1, GFX_ALL },
{ BRW_OPCODE_FBH, 75, "fbh", 1, 1, GEN_GE(GFX7) }, { BRW_OPCODE_FBH, 75, "fbh", 1, 1, GFX_GE(GFX7) },
{ BRW_OPCODE_FBL, 76, "fbl", 1, 1, GEN_GE(GFX7) }, { BRW_OPCODE_FBL, 76, "fbl", 1, 1, GFX_GE(GFX7) },
{ BRW_OPCODE_CBIT, 77, "cbit", 1, 1, GEN_GE(GFX7) }, { BRW_OPCODE_CBIT, 77, "cbit", 1, 1, GFX_GE(GFX7) },
{ BRW_OPCODE_ADDC, 78, "addc", 2, 1, GEN_GE(GFX7) }, { BRW_OPCODE_ADDC, 78, "addc", 2, 1, GFX_GE(GFX7) },
{ BRW_OPCODE_SUBB, 79, "subb", 2, 1, GEN_GE(GFX7) }, { BRW_OPCODE_SUBB, 79, "subb", 2, 1, GFX_GE(GFX7) },
{ BRW_OPCODE_SAD2, 80, "sad2", 2, 1, GEN_ALL }, { BRW_OPCODE_SAD2, 80, "sad2", 2, 1, GFX_ALL },
{ BRW_OPCODE_SADA2, 81, "sada2", 2, 1, GEN_ALL }, { BRW_OPCODE_SADA2, 81, "sada2", 2, 1, GFX_ALL },
{ BRW_OPCODE_DP4, 84, "dp4", 2, 1, GEN_LT(GFX11) }, { BRW_OPCODE_DP4, 84, "dp4", 2, 1, GFX_LT(GFX11) },
{ BRW_OPCODE_DPH, 85, "dph", 2, 1, GEN_LT(GFX11) }, { BRW_OPCODE_DPH, 85, "dph", 2, 1, GFX_LT(GFX11) },
{ BRW_OPCODE_DP3, 86, "dp3", 2, 1, GEN_LT(GFX11) }, { BRW_OPCODE_DP3, 86, "dp3", 2, 1, GFX_LT(GFX11) },
{ BRW_OPCODE_DP2, 87, "dp2", 2, 1, GEN_LT(GFX11) }, { BRW_OPCODE_DP2, 87, "dp2", 2, 1, GFX_LT(GFX11) },
{ BRW_OPCODE_LINE, 89, "line", 2, 1, GEN_LE(GFX10) }, { BRW_OPCODE_LINE, 89, "line", 2, 1, GFX_LE(GFX10) },
{ BRW_OPCODE_PLN, 90, "pln", 2, 1, GEN_GE(GFX45) & GEN_LE(GFX10) }, { BRW_OPCODE_PLN, 90, "pln", 2, 1, GFX_GE(GFX45) & GFX_LE(GFX10) },
{ BRW_OPCODE_MAD, 91, "mad", 3, 1, GEN_GE(GFX6) }, { BRW_OPCODE_MAD, 91, "mad", 3, 1, GFX_GE(GFX6) },
{ BRW_OPCODE_LRP, 92, "lrp", 3, 1, GEN_GE(GFX6) & GEN_LE(GFX10) }, { BRW_OPCODE_LRP, 92, "lrp", 3, 1, GFX_GE(GFX6) & GFX_LE(GFX10) },
{ BRW_OPCODE_MADM, 93, "madm", 3, 1, GEN_GE(GFX8) }, { BRW_OPCODE_MADM, 93, "madm", 3, 1, GFX_GE(GFX8) },
{ BRW_OPCODE_NENOP, 125, "nenop", 0, 0, GFX45 }, { BRW_OPCODE_NENOP, 125, "nenop", 0, 0, GFX45 },
{ BRW_OPCODE_NOP, 126, "nop", 0, 0, GEN_LT(GFX12) }, { BRW_OPCODE_NOP, 126, "nop", 0, 0, GFX_LT(GFX12) },
{ BRW_OPCODE_NOP, 96, "nop", 0, 0, GEN_GE(GFX12) } { BRW_OPCODE_NOP, 96, "nop", 0, 0, GFX_GE(GFX12) }
}; };
/** /**

8
src/intel/compiler/brw_gen_enum.h
View File

@@ -37,12 +37,12 @@ enum gen {
GFX11 = (1 << 9), GFX11 = (1 << 9),
GFX12 = (1 << 10), GFX12 = (1 << 10),
GFX125 = (1 << 11), GFX125 = (1 << 11),
GEN_ALL = ~0 GFX_ALL = ~0
}; };
#define GEN_LT(gen) ((gen) - 1) #define GFX_LT(gen) ((gen) - 1)
#define GEN_GE(gen) (~GEN_LT(gen)) #define GFX_GE(gen) (~GFX_LT(gen))
#define GEN_LE(gen) (GEN_LT(gen) | (gen)) #define GFX_LE(gen) (GFX_LT(gen) | (gen))
static enum gen static enum gen
gen_from_devinfo(const struct gen_device_info *devinfo) gen_from_devinfo(const struct gen_device_info *devinfo)

18
src/intel/compiler/test_eu_compact.cpp
View File

@@ -273,15 +273,15 @@ struct {
void (*func)(struct brw_codegen *p); void (*func)(struct brw_codegen *p);
int gens; int gens;
} tests[] = { } tests[] = {
{ gen_MOV_GRF_GRF, GEN_ALL }, { gen_MOV_GRF_GRF, GFX_ALL },
{ gen_ADD_GRF_GRF_GRF, GEN_ALL }, { gen_ADD_GRF_GRF_GRF, GFX_ALL },
{ gen_ADD_GRF_GRF_IMM, GEN_ALL }, { gen_ADD_GRF_GRF_IMM, GFX_ALL },
{ gen_ADD_GRF_GRF_IMM_d, GEN_ALL }, { gen_ADD_GRF_GRF_IMM_d, GFX_ALL },
{ gen_ADD_MRF_GRF_GRF, GEN_LE(GFX6) }, { gen_ADD_MRF_GRF_GRF, GFX_LE(GFX6) },
{ gen_ADD_vec1_GRF_GRF_GRF, GEN_ALL }, { gen_ADD_vec1_GRF_GRF_GRF, GFX_ALL },
{ gen_PLN_MRF_GRF_GRF, GEN_LE(GFX6) }, { gen_PLN_MRF_GRF_GRF, GFX_LE(GFX6) },
{ gen_f0_0_MOV_GRF_GRF, GEN_ALL }, { gen_f0_0_MOV_GRF_GRF, GFX_ALL },
{ gen_f0_1_MOV_GRF_GRF, GEN_ALL }, { gen_f0_1_MOV_GRF_GRF, GFX_ALL },
}; };
static bool static bool