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radv: Add named constants for max framebuffer width/height.

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13721>
This commit is contained in:
Bas Nieuwenhuizen
2021-11-21 02:01:46 +01:00
committed by Marge Bot
parent 4c703686db
commit 6968c87e97
3 changed files with 10 additions and 6 deletions
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2
src/amd/vulkan/radv_constants.h
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@@ -55,6 +55,8 @@
#define NUM_DEPTH_CLEAR_PIPELINES 2 #define NUM_DEPTH_CLEAR_PIPELINES 2
#define NUM_DEPTH_DECOMPRESS_PIPELINES 3 #define NUM_DEPTH_DECOMPRESS_PIPELINES 3
#define MAX_FRAMEBUFFER_WIDTH (1u << 14)
#define MAX_FRAMEBUFFER_HEIGHT (1u << 14)
/* /*
* This is the point we switch from using CP to compute shader * This is the point we switch from using CP to compute shader

4
src/amd/vulkan/radv_device.c
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@@ -1771,8 +1771,8 @@ radv_GetPhysicalDeviceProperties(VkPhysicalDevice physicalDevice,
.minInterpolationOffset = -2, .minInterpolationOffset = -2,
.maxInterpolationOffset = 2, .maxInterpolationOffset = 2,
.subPixelInterpolationOffsetBits = 8, .subPixelInterpolationOffsetBits = 8,
.maxFramebufferWidth = (1 << 14), .maxFramebufferWidth = MAX_FRAMEBUFFER_WIDTH,
.maxFramebufferHeight = (1 << 14), .maxFramebufferHeight = MAX_FRAMEBUFFER_HEIGHT,
.maxFramebufferLayers = (1 << 10), .maxFramebufferLayers = (1 << 10),
.framebufferColorSampleCounts = sample_counts, .framebufferColorSampleCounts = sample_counts,
.framebufferDepthSampleCounts = sample_counts, .framebufferDepthSampleCounts = sample_counts,

10
src/amd/vulkan/si_cmd_buffer.c
View File

@@ -234,11 +234,13 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
S_028204_WINDOW_OFFSET_DISABLE(1)); S_028204_WINDOW_OFFSET_DISABLE(1));
radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
S_028240_WINDOW_OFFSET_DISABLE(1)); S_028240_WINDOW_OFFSET_DISABLE(1));
radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR, radeon_set_context_reg(
S_028244_BR_X(16384) | S_028244_BR_Y(16384)); cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
S_028244_BR_X(MAX_FRAMEBUFFER_WIDTH) | S_028244_BR_Y(MAX_FRAMEBUFFER_HEIGHT));
radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0); radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR, radeon_set_context_reg(
S_028034_BR_X(16384) | S_028034_BR_Y(16384)); cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
S_028034_BR_X(MAX_FRAMEBUFFER_WIDTH) | S_028034_BR_Y(MAX_FRAMEBUFFER_HEIGHT));
} }
if (!has_clear_state) { if (!has_clear_state) {