OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

anv: get rid of the second dynamic state heap

Browse Source 
Pretty big change... Sorry for that.

I can't exactly remember why I created 2 heaps. I think it's because I
mistakenly thought the samplers in the binding sampler pointers needed
to be indexed from the binding table. But that's not the case, they
just need to be in the dynamic state heap.

In the future, this change will allow to also allocate buffers for
push constant data in the newly created dynamic_visible_pool which
will be useful on < Gfx12.0 where this is the only place push constant
data can live for compute shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30047>
This commit is contained in:
Lionel Landwerlin
2024-07-05 16:22:10 +03:00
committed by Marge Bot
parent 355a1f2058
commit 692e1ab2c1
13 changed files with 110 additions and 350 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/intel/vulkan/anv_batch_chain.c
View File

@@ -749,13 +749,8 @@ anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
{
if (size == 0)
return ANV_STATE_NULL;
assert(cmd_buffer->state.current_db_mode !=
ANV_CMD_DESCRIPTOR_BUFFER_MODE_UNKNOWN);
struct anv_state state =
anv_state_stream_alloc(cmd_buffer->state.current_db_mode ==
ANV_CMD_DESCRIPTOR_BUFFER_MODE_BUFFER ?
&cmd_buffer->dynamic_state_db_stream :
&cmd_buffer->dynamic_state_stream,
anv_state_stream_alloc(&cmd_buffer->dynamic_state_stream,
size, alignment);
if (state.map == NULL)
anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_DEVICE_MEMORY);

14
src/intel/vulkan/anv_blorp.c
View File

@@ -98,14 +98,9 @@ upload_dynamic_state(struct blorp_context *context,
{
struct anv_device *device = context->driver_ctx;
device->blorp.dynamic_states[name].state =
device->blorp.dynamic_states[name] =
anv_state_pool_emit_data(&device->dynamic_state_pool,
size, alignment, data);
if (device->vk.enabled_extensions.EXT_descriptor_buffer) {
device->blorp.dynamic_states[name].db_state =
anv_state_pool_emit_data(&device->dynamic_state_db_pool,
size, alignment, data);
}
}
void
@@ -138,12 +133,7 @@ anv_device_finish_blorp(struct anv_device *device)
*/
for (uint32_t i = 0; i < ARRAY_SIZE(device->blorp.dynamic_states); i++) {
anv_state_pool_free(&device->dynamic_state_pool,
device->blorp.dynamic_states[i].state);
if (device->vk.enabled_extensions.EXT_descriptor_buffer) {
anv_state_pool_free(&device->dynamic_state_db_pool,
device->blorp.dynamic_states[i].db_state);
}
device->blorp.dynamic_states[i]);
}
#endif
blorp_finish(&device->blorp.context);

13
src/intel/vulkan/anv_cmd_buffer.c
View File

@@ -151,8 +151,6 @@ anv_create_cmd_buffer(struct vk_command_pool *pool,
&device->internal_surface_state_pool, 4096);
anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
&device->dynamic_state_pool, 16384);
anv_state_stream_init(&cmd_buffer->dynamic_state_db_stream,
&device->dynamic_state_db_pool, 16384);
anv_state_stream_init(&cmd_buffer->general_state_stream,
&device->general_state_pool, 16384);
anv_state_stream_init(&cmd_buffer->indirect_push_descriptor_stream,
@@ -206,7 +204,6 @@ destroy_cmd_buffer(struct anv_cmd_buffer *cmd_buffer)
anv_state_stream_finish(&cmd_buffer->surface_state_stream);
anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
anv_state_stream_finish(&cmd_buffer->dynamic_state_db_stream);
anv_state_stream_finish(&cmd_buffer->general_state_stream);
anv_state_stream_finish(&cmd_buffer->indirect_push_descriptor_stream);
anv_state_stream_finish(&cmd_buffer->push_descriptor_buffer_stream);
@@ -272,10 +269,6 @@ reset_cmd_buffer(struct anv_cmd_buffer *cmd_buffer,
anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
&cmd_buffer->device->dynamic_state_pool, 16384);
anv_state_stream_finish(&cmd_buffer->dynamic_state_db_stream);
anv_state_stream_init(&cmd_buffer->dynamic_state_db_stream,
&cmd_buffer->device->dynamic_state_db_pool, 16384);
anv_state_stream_finish(&cmd_buffer->general_state_stream);
anv_state_stream_init(&cmd_buffer->general_state_stream,
&cmd_buffer->device->general_state_pool, 16384);
@@ -999,9 +992,9 @@ void anv_CmdBindDescriptorBuffersEXT(
struct anv_cmd_state *state = &cmd_buffer->state;
for (uint32_t i = 0; i < bufferCount; i++) {
assert(pBindingInfos[i].address >= cmd_buffer->device->physical->va.descriptor_buffer_pool.addr &&
pBindingInfos[i].address < (cmd_buffer->device->physical->va.descriptor_buffer_pool.addr +
cmd_buffer->device->physical->va.descriptor_buffer_pool.size));
assert(pBindingInfos[i].address >= cmd_buffer->device->physical->va.dynamic_visible_pool.addr &&
pBindingInfos[i].address < (cmd_buffer->device->physical->va.dynamic_visible_pool.addr +
cmd_buffer->device->physical->va.dynamic_visible_pool.size));
if (state->descriptor_buffers.address[i] != pBindingInfos[i].address) {
state->descriptor_buffers.address[i] = pBindingInfos[i].address;

9
src/intel/vulkan/anv_descriptor_set.c
View File

@@ -1319,7 +1319,7 @@ anv_descriptor_pool_heap_init(struct anv_device *device,
ANV_BO_ALLOC_MAPPED |
ANV_BO_ALLOC_HOST_CACHED_COHERENT |
(samplers ?
ANV_BO_ALLOC_SAMPLER_POOL :
ANV_BO_ALLOC_DYNAMIC_VISIBLE_POOL :
ANV_BO_ALLOC_DESCRIPTOR_POOL),
0 /* explicit_address */,
&heap->bo);
@@ -2133,8 +2133,6 @@ anv_sampler_state_for_descriptor_set(const struct anv_sampler *sampler,
const struct anv_descriptor_set *set,
uint32_t plane)
{
if (set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_DESCRIPTOR_BUFFER_BIT_EXT)
return sampler->db_state[plane];
return sampler->state[plane];
}
@@ -2901,7 +2899,7 @@ void anv_GetDescriptorEXT(
case VK_DESCRIPTOR_TYPE_SAMPLER:
if (pDescriptorInfo->data.pSampler &&
(sampler = anv_sampler_from_handle(*pDescriptorInfo->data.pSampler))) {
memcpy(pDescriptor, sampler->db_state[0], ANV_SAMPLER_STATE_SIZE);
memcpy(pDescriptor, sampler->state[0], ANV_SAMPLER_STATE_SIZE);
} else {
memset(pDescriptor, 0, ANV_SAMPLER_STATE_SIZE);
}
@@ -2932,8 +2930,7 @@ void anv_GetDescriptorEXT(
(sampler = anv_sampler_from_handle(
pDescriptorInfo->data.pCombinedImageSampler->sampler))) {
memcpy(pDescriptor + desc_offset + ANV_SURFACE_STATE_SIZE,
sampler->db_state[i],
ANV_SAMPLER_STATE_SIZE);
sampler->state[i], ANV_SAMPLER_STATE_SIZE);
} else {
memset(pDescriptor + desc_offset + ANV_SURFACE_STATE_SIZE,
0, ANV_SAMPLER_STATE_SIZE);

131
src/intel/vulkan/anv_device.c
View File

@@ -1643,12 +1643,12 @@ get_properties(const struct anv_physical_device *pdevice,
props->robustStorageBufferDescriptorSize = ANV_SURFACE_STATE_SIZE;
props->inputAttachmentDescriptorSize = ANV_SURFACE_STATE_SIZE;
props->accelerationStructureDescriptorSize = sizeof(struct anv_address_range_descriptor);
props->maxSamplerDescriptorBufferRange = pdevice->va.descriptor_buffer_pool.size;
props->maxSamplerDescriptorBufferRange = pdevice->va.dynamic_visible_pool.size;
props->maxResourceDescriptorBufferRange = anv_physical_device_bindless_heap_size(pdevice,
true);
props->resourceDescriptorBufferAddressSpaceSize = pdevice->va.descriptor_buffer_pool.size;
props->descriptorBufferAddressSpaceSize = pdevice->va.descriptor_buffer_pool.size;
props->samplerDescriptorBufferAddressSpaceSize = pdevice->va.descriptor_buffer_pool.size;
props->resourceDescriptorBufferAddressSpaceSize = pdevice->va.dynamic_visible_pool.size;
props->descriptorBufferAddressSpaceSize = pdevice->va.dynamic_visible_pool.size;
props->samplerDescriptorBufferAddressSpaceSize = pdevice->va.dynamic_visible_pool.size;
}
/* VK_EXT_extended_dynamic_state3 */
@@ -2062,7 +2062,7 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
device->memory.default_buffer_mem_types =
BITFIELD_RANGE(0, device->memory.type_count);
device->memory.protected_mem_types = 0;
device->memory.desc_buffer_mem_types = 0;
device->memory.dynamic_visible_mem_types = 0;
device->memory.compressed_mem_types = 0;
const uint32_t base_types_count = device->memory.type_count;
@@ -2085,13 +2085,13 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
if (skip)
continue;
device->memory.desc_buffer_mem_types |=
device->memory.dynamic_visible_mem_types |=
BITFIELD_BIT(device->memory.type_count);
struct anv_memory_type *new_type =
&device->memory.types[device->memory.type_count++];
*new_type = device->memory.types[i];
new_type->descriptor_buffer = true;
new_type->dynamic_visible = true;
}
assert(device->memory.type_count <= VK_MAX_MEMORY_TYPES);
@@ -3091,11 +3091,6 @@ anv_device_init_border_colors(struct anv_device *device)
device->border_colors =
anv_state_pool_emit_data(&device->dynamic_state_pool,
sizeof(border_colors), 64, border_colors);
if (device->vk.enabled_extensions.EXT_descriptor_buffer) {
device->border_colors_db =
anv_state_pool_emit_data(&device->dynamic_state_db_pool,
sizeof(border_colors), 64, border_colors);
}
}
static VkResult
@@ -3152,9 +3147,6 @@ decode_get_bo(void *v_batch, bool ppgtt, uint64_t address)
if (get_bo_from_pool(&ret_bo, &device->dynamic_state_pool.block_pool, address))
return ret_bo;
if (device->vk.enabled_extensions.EXT_descriptor_buffer &&
get_bo_from_pool(&ret_bo, &device->dynamic_state_db_pool.block_pool, address))
return ret_bo;
if (get_bo_from_pool(&ret_bo, &device->instruction_state_pool.block_pool, address))
return ret_bo;
if (get_bo_from_pool(&ret_bo, &device->binding_table_pool.block_pool, address))
@@ -3495,13 +3487,9 @@ VkResult anv_CreateDevice(
/* Always initialized because the the memory types point to this and they
* are on the physical device.
*/
util_vma_heap_init(&device->vma_desc_buf,
device->physical->va.descriptor_buffer_pool.addr,
device->physical->va.descriptor_buffer_pool.size);
util_vma_heap_init(&device->vma_samplers,
device->physical->va.sampler_state_pool.addr,
device->physical->va.sampler_state_pool.size);
util_vma_heap_init(&device->vma_dynamic_visible,
device->physical->va.dynamic_visible_pool.addr,
device->physical->va.dynamic_visible_pool.size);
util_vma_heap_init(&device->vma_trtt,
device->physical->va.trtt.addr,
device->physical->va.trtt.size);
@@ -3572,18 +3560,6 @@ VkResult anv_CreateDevice(
if (result != VK_SUCCESS)
goto fail_general_state_pool;
if (device->vk.enabled_extensions.EXT_descriptor_buffer) {
result = anv_state_pool_init(&device->dynamic_state_db_pool, device,
&(struct anv_state_pool_params) {
.name = "dynamic pool (db)",
.base_address = device->physical->va.dynamic_state_db_pool.addr,
.block_size = 16384,
.max_size = device->physical->va.dynamic_state_db_pool.size,
});
if (result != VK_SUCCESS)
goto fail_dynamic_state_pool;
}
/* The border color pointer is limited to 24 bits, so we need to make
* sure that any such color used at any point in the program doesn't
* exceed that limit.
@@ -3595,16 +3571,7 @@ VkResult anv_CreateDevice(
MAX_CUSTOM_BORDER_COLORS,
sizeof(struct gfx8_border_color), 64);
if (result != VK_SUCCESS)
goto fail_dynamic_state_db_pool;
if (device->vk.enabled_extensions.EXT_descriptor_buffer) {
result = anv_state_reserved_array_pool_init(&device->custom_border_colors_db,
&device->dynamic_state_db_pool,
MAX_CUSTOM_BORDER_COLORS,
sizeof(struct gfx8_border_color), 64);
if (result != VK_SUCCESS)
goto fail_custom_border_color_pool;
}
goto fail_dynamic_state_pool;
result = anv_state_pool_init(&device->instruction_state_pool, device,
&(struct anv_state_pool_params) {
@@ -3614,7 +3581,7 @@ VkResult anv_CreateDevice(
.max_size = device->physical->va.instruction_state_pool.size,
});
if (result != VK_SUCCESS)
goto fail_reserved_array_pool;
goto fail_custom_border_color_pool;
if (device->info->verx10 >= 125) {
/* Put the scratch surface states at the beginning of the internal
@@ -3820,17 +3787,6 @@ VkResult anv_CreateDevice(
goto fail_trivial_batch;
anv_genX(device->info, init_cps_device_state)(device);
if (device->vk.enabled_extensions.EXT_descriptor_buffer) {
device->cps_states_db =
anv_state_pool_alloc(&device->dynamic_state_db_pool,
device->cps_states.alloc_size, 32);
if (device->cps_states_db.map == NULL)
goto fail_trivial_batch;
memcpy(device->cps_states_db.map, device->cps_states.map,
device->cps_states.alloc_size);
}
}
if (device->physical->indirect_descriptors) {
@@ -4089,14 +4045,8 @@ VkResult anv_CreateDevice(
anv_state_pool_finish(&device->scratch_surface_state_pool);
fail_instruction_state_pool:
anv_state_pool_finish(&device->instruction_state_pool);
fail_reserved_array_pool:
if (device->vk.enabled_extensions.EXT_descriptor_buffer)
anv_state_reserved_array_pool_finish(&device->custom_border_colors_db);
fail_custom_border_color_pool:
anv_state_reserved_array_pool_finish(&device->custom_border_colors);
fail_dynamic_state_db_pool:
if (device->vk.enabled_extensions.EXT_descriptor_buffer)
anv_state_pool_finish(&device->dynamic_state_db_pool);
fail_dynamic_state_pool:
anv_state_pool_finish(&device->dynamic_state_pool);
fail_general_state_pool:
@@ -4112,8 +4062,7 @@ VkResult anv_CreateDevice(
pthread_mutex_destroy(&device->mutex);
fail_vmas:
util_vma_heap_finish(&device->vma_trtt);
util_vma_heap_finish(&device->vma_samplers);
util_vma_heap_finish(&device->vma_desc_buf);
util_vma_heap_finish(&device->vma_dynamic_visible);
util_vma_heap_finish(&device->vma_desc);
util_vma_heap_finish(&device->vma_hi);
util_vma_heap_finish(&device->vma_lo);
@@ -4183,9 +4132,6 @@ void anv_DestroyDevice(
}
anv_state_reserved_array_pool_finish(&device->custom_border_colors);
if (device->vk.enabled_extensions.EXT_descriptor_buffer)
anv_state_reserved_array_pool_finish(&device->custom_border_colors_db);
#ifdef HAVE_VALGRIND
/* We only need to free these to prevent valgrind errors. The backing
* BO will go away in a couple of lines so we don't actually leak.
@@ -4194,11 +4140,6 @@ void anv_DestroyDevice(
anv_state_pool_free(&device->dynamic_state_pool, device->slice_hash);
anv_state_pool_free(&device->dynamic_state_pool, device->cps_states);
anv_state_pool_free(&device->dynamic_state_pool, device->breakpoint);
if (device->vk.enabled_extensions.EXT_descriptor_buffer) {
anv_state_pool_free(&device->dynamic_state_db_pool, device->cps_states_db);
anv_state_pool_free(&device->dynamic_state_db_pool, device->slice_hash_db);
anv_state_pool_free(&device->dynamic_state_db_pool, device->border_colors_db);
}
#endif
for (unsigned i = 0; i < ARRAY_SIZE(device->rt_scratch_bos); i++) {
@@ -4238,8 +4179,6 @@ void anv_DestroyDevice(
if (device->physical->indirect_descriptors)
anv_state_pool_finish(&device->bindless_surface_state_pool);
anv_state_pool_finish(&device->instruction_state_pool);
if (device->vk.enabled_extensions.EXT_descriptor_buffer)
anv_state_pool_finish(&device->dynamic_state_db_pool);
anv_state_pool_finish(&device->dynamic_state_pool);
anv_state_pool_finish(&device->general_state_pool);
@@ -4250,8 +4189,7 @@ void anv_DestroyDevice(
anv_bo_cache_finish(&device->bo_cache);
util_vma_heap_finish(&device->vma_trtt);
util_vma_heap_finish(&device->vma_samplers);
util_vma_heap_finish(&device->vma_desc_buf);
util_vma_heap_finish(&device->vma_dynamic_visible);
util_vma_heap_finish(&device->vma_desc);
util_vma_heap_finish(&device->vma_hi);
util_vma_heap_finish(&device->vma_lo);
@@ -4313,17 +4251,14 @@ anv_vma_heap_for_flags(struct anv_device *device,
if (alloc_flags & ANV_BO_ALLOC_TRTT)
return &device->vma_trtt;
if (alloc_flags & ANV_BO_ALLOC_DESCRIPTOR_BUFFER_POOL)
return &device->vma_desc_buf;
if (alloc_flags & ANV_BO_ALLOC_32BIT_ADDRESS)
return &device->vma_lo;
if (alloc_flags & ANV_BO_ALLOC_DESCRIPTOR_POOL)
return &device->vma_desc;
if (alloc_flags & ANV_BO_ALLOC_SAMPLER_POOL)
return &device->vma_samplers;
if (alloc_flags & ANV_BO_ALLOC_DYNAMIC_VISIBLE_POOL)
return &device->vma_dynamic_visible;
return &device->vma_hi;
}
@@ -4342,7 +4277,7 @@ anv_vma_alloc(struct anv_device *device,
if (alloc_flags & ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS) {
assert(*out_vma_heap == &device->vma_hi ||
*out_vma_heap == &device->vma_desc_buf ||
*out_vma_heap == &device->vma_dynamic_visible ||
*out_vma_heap == &device->vma_trtt);
if (client_address) {
@@ -4378,8 +4313,7 @@ anv_vma_free(struct anv_device *device,
assert(vma_heap == &device->vma_lo ||
vma_heap == &device->vma_hi ||
vma_heap == &device->vma_desc ||
vma_heap == &device->vma_desc_buf ||
vma_heap == &device->vma_samplers ||
vma_heap == &device->vma_dynamic_visible ||
vma_heap == &device->vma_trtt);
const uint64_t addr_48b = intel_48b_address(address);
@@ -4564,8 +4498,8 @@ VkResult anv_AllocateMemory(
if (!(alloc_flags & ANV_BO_ALLOC_EXTERNAL) && mem_type->compressed)
alloc_flags |= ANV_BO_ALLOC_COMPRESSED;
if (mem_type->descriptor_buffer)
alloc_flags |= ANV_BO_ALLOC_DESCRIPTOR_BUFFER_POOL;
if (mem_type->dynamic_visible)
alloc_flags |= ANV_BO_ALLOC_DYNAMIC_VISIBLE_POOL;
if (mem->vk.ahardware_buffer) {
result = anv_import_ahw_memory(_device, mem);
@@ -5126,13 +5060,14 @@ anv_get_buffer_memory_requirements(struct anv_device *device,
*
* We have special memory types for descriptor buffers.
*/
uint32_t memory_types =
(flags & VK_BUFFER_CREATE_PROTECTED_BIT) ?
device->physical->memory.protected_mem_types :
((usage & (VK_BUFFER_USAGE_RESOURCE_DESCRIPTOR_BUFFER_BIT_EXT |
VK_BUFFER_USAGE_SAMPLER_DESCRIPTOR_BUFFER_BIT_EXT)) ?
device->physical->memory.desc_buffer_mem_types :
device->physical->memory.default_buffer_mem_types);
uint32_t memory_types;
if (flags & VK_BUFFER_CREATE_PROTECTED_BIT)
memory_types = device->physical->memory.protected_mem_types;
else if (usage & (VK_BUFFER_USAGE_RESOURCE_DESCRIPTOR_BUFFER_BIT_EXT |
VK_BUFFER_USAGE_SAMPLER_DESCRIPTOR_BUFFER_BIT_EXT))
memory_types = device->physical->memory.dynamic_visible_mem_types;
else
memory_types = device->physical->memory.default_buffer_mem_types;
/* The GPU appears to write back to main memory in cachelines. Writes to a
* buffers should not clobber with writes to another buffers so make sure
@@ -5372,11 +5307,11 @@ VkResult anv_GetSamplerOpaqueCaptureDescriptorDataEXT(
ANV_FROM_HANDLE(anv_device, device, _device);
ANV_FROM_HANDLE(anv_sampler, sampler, pInfo->sampler);
if (sampler->custom_border_color_db.alloc_size != 0) {
if (sampler->custom_border_color.alloc_size != 0) {
*((uint32_t *)pData) =
anv_state_reserved_array_pool_state_index(
&device->custom_border_colors_db,
sampler->custom_border_color_db);
&device->custom_border_colors,
sampler->custom_border_color);
} else {
*((uint32_t *)pData) = 0;
}
@@ -5404,10 +5339,6 @@ void anv_DestroySampler(
anv_state_reserved_array_pool_free(&device->custom_border_colors,
sampler->custom_border_color);
}
if (sampler->custom_border_color_db.map) {
anv_state_reserved_array_pool_free(&device->custom_border_colors_db,
sampler->custom_border_color_db);
}
vk_sampler_destroy(&device->vk, pAllocator, &sampler->vk);
}

8
src/intel/vulkan/anv_pipeline_cache.c
View File

@@ -53,8 +53,8 @@ static void
anv_embedded_sampler_free(struct anv_device *device,
struct anv_embedded_sampler *sampler)
{
anv_state_pool_free(&device->dynamic_state_db_pool, sampler->sampler_state);
anv_state_pool_free(&device->dynamic_state_db_pool, sampler->border_color_state);
anv_state_pool_free(&device->dynamic_state_pool, sampler->sampler_state);
anv_state_pool_free(&device->dynamic_state_pool, sampler->border_color_state);
vk_free(&device->vk.alloc, sampler);
}
@@ -318,10 +318,10 @@ anv_shader_bin_create(struct anv_device *device,
int rv_count = 0;
struct brw_shader_reloc_value reloc_values[9];
assert((device->physical->va.descriptor_buffer_pool.addr & 0xffffffff) == 0);
assert((device->physical->va.dynamic_visible_pool.addr & 0xffffffff) == 0);
reloc_values[rv_count++] = (struct brw_shader_reloc_value) {
.id = BRW_SHADER_RELOC_DESCRIPTORS_BUFFER_ADDR_HIGH,
.value = device->physical->va.descriptor_buffer_pool.addr >> 32,
.value = device->physical->va.dynamic_visible_pool.addr >> 32,
};
assert((device->physical->va.indirect_descriptor_pool.addr & 0xffffffff) == 0);
assert((device->physical->va.internal_surface_state_pool.addr & 0xffffffff) == 0);

52
src/intel/vulkan/anv_private.h
View File

@@ -425,8 +425,8 @@ enum anv_bo_alloc_flags {
/** Specifies that the BO should be cached and incoherent. */
ANV_BO_ALLOC_HOST_CACHED = (1 << 16),
/** For sampler pools */
ANV_BO_ALLOC_SAMPLER_POOL = (1 << 17),
/** For buffer addressable from the dynamic state heap */
ANV_BO_ALLOC_DYNAMIC_VISIBLE_POOL = (1 << 17),
/** Specifies that the BO is imported.
*
@@ -444,11 +444,8 @@ enum anv_bo_alloc_flags {
*/
ANV_BO_ALLOC_AUX_CCS = (1 << 20),
/** For descriptor buffer pools */
ANV_BO_ALLOC_DESCRIPTOR_BUFFER_POOL = (1 << 21),
/** Compressed buffer, only supported in Xe2+ */
ANV_BO_ALLOC_COMPRESSED = (1 << 22),
ANV_BO_ALLOC_COMPRESSED = (1 << 21),
};
/** Specifies that the BO should be cached and coherent. */
@@ -958,8 +955,8 @@ struct anv_memory_type {
/* Standard bits passed on to the client */
VkMemoryPropertyFlags propertyFlags;
uint32_t heapIndex;
/* Whether this is the descriptor buffer memory type */
bool descriptor_buffer;
/* Whether this is the dynamic visible memory type */
bool dynamic_visible;
bool compressed;
};
@@ -1116,8 +1113,8 @@ struct anv_physical_device {
#endif
/** Mask of memory types of normal allocations */
uint32_t default_buffer_mem_types;
/** Mask of memory types of descriptor buffers */
uint32_t desc_buffer_mem_types;
/** Mask of memory types of data indexable from the dynamic heap */
uint32_t dynamic_visible_mem_types;
/** Mask of memory types of protected buffers/images */
uint32_t protected_mem_types;
/** Mask of memory types of compressed buffers/images */
@@ -1155,9 +1152,9 @@ struct anv_physical_device {
*/
struct anv_va_range dynamic_state_pool;
/**
* Sampler state pool
* Buffer pool that can be index from the dynamic state heap
*/
struct anv_va_range sampler_state_pool;
struct anv_va_range dynamic_visible_pool;
/**
* Indirect descriptor pool
*/
@@ -1170,14 +1167,6 @@ struct anv_physical_device {
* Instruction state pool
*/
struct anv_va_range instruction_state_pool;
/**
* Dynamic state pool when using descriptor buffers
*/
struct anv_va_range dynamic_state_db_pool;
/**
* Descriptor buffers
*/
struct anv_va_range descriptor_buffer_pool;
/**
* Push descriptor with descriptor buffers
*/
@@ -1247,7 +1236,7 @@ anv_physical_device_bindless_heap_size(const struct anv_physical_device *device,
*/
return device->uses_ex_bso ?
(descriptor_buffer ?
device->va.descriptor_buffer_pool.size :
device->va.dynamic_visible_pool.size :
device->va.bindless_surface_state_pool.size) :
64 * 1024 * 1024 /* 64 MiB */;
}
@@ -1806,8 +1795,7 @@ struct anv_device {
struct util_vma_heap vma_lo;
struct util_vma_heap vma_hi;
struct util_vma_heap vma_desc;
struct util_vma_heap vma_desc_buf;
struct util_vma_heap vma_samplers;
struct util_vma_heap vma_dynamic_visible;
struct util_vma_heap vma_trtt;
/** List of all anv_device_memory objects */
@@ -1832,7 +1820,6 @@ struct anv_device {
struct anv_state_pool general_state_pool;
struct anv_state_pool aux_tt_pool;
struct anv_state_pool dynamic_state_pool;
struct anv_state_pool dynamic_state_db_pool;
struct anv_state_pool instruction_state_pool;
struct anv_state_pool binding_table_pool;
struct anv_state_pool scratch_surface_state_pool;
@@ -1842,7 +1829,6 @@ struct anv_device {
struct anv_state_pool push_descriptor_buffer_pool;
struct anv_state_reserved_array_pool custom_border_colors;
struct anv_state_reserved_array_pool custom_border_colors_db;
/** BO used for various workarounds
*
@@ -1878,17 +1864,12 @@ struct anv_device {
struct {
struct blorp_context context;
struct {
struct anv_state state;
struct anv_state db_state;
} dynamic_states[BLORP_DYNAMIC_STATE_COUNT];
struct anv_state dynamic_states[BLORP_DYNAMIC_STATE_COUNT];
} blorp;
struct anv_state border_colors;
struct anv_state border_colors_db;
struct anv_state slice_hash;
struct anv_state slice_hash_db;
/** An array of CPS_STATE structures grouped by MAX_VIEWPORTS elements
*
@@ -1899,7 +1880,6 @@ struct anv_device {
* array.
*/
struct anv_state cps_states;
struct anv_state cps_states_db;
uint32_t queue_count;
struct anv_queue * queues;
@@ -4065,7 +4045,6 @@ struct anv_cmd_buffer {
/* Stream objects for storing temporary data */
struct anv_state_stream surface_state_stream;
struct anv_state_stream dynamic_state_stream;
struct anv_state_stream dynamic_state_db_stream;
struct anv_state_stream general_state_stream;
struct anv_state_stream indirect_push_descriptor_stream;
struct anv_state_stream push_descriptor_buffer_stream;
@@ -4230,11 +4209,6 @@ static inline struct anv_address
anv_cmd_buffer_dynamic_state_address(struct anv_cmd_buffer *cmd_buffer,
struct anv_state state)
{
if (cmd_buffer->state.current_db_mode ==
ANV_CMD_DESCRIPTOR_BUFFER_MODE_BUFFER) {
return anv_state_pool_state_address(
&cmd_buffer->device->dynamic_state_db_pool, state);
}
return anv_state_pool_state_address(
&cmd_buffer->device->dynamic_state_pool, state);
}
@@ -5994,7 +5968,6 @@ struct anv_sampler {
unsigned char sha1[20];
uint32_t state[3][4];
uint32_t db_state[3][4];
/* Packed SAMPLER_STATE without the border color pointer. */
uint32_t state_no_bc[3][4];
uint32_t n_planes;
@@ -6005,7 +5978,6 @@ struct anv_sampler {
struct anv_state bindless_state;
struct anv_state custom_border_color;
struct anv_state custom_border_color_db;
};

24
src/intel/vulkan/anv_va.c
View File

@@ -52,8 +52,6 @@ anv_device_print_vas(struct anv_physical_device *device)
#name);
PRINT_HEAP(general_state_pool);
PRINT_HEAP(low_heap);
PRINT_HEAP(dynamic_state_pool);
PRINT_HEAP(sampler_state_pool);
PRINT_HEAP(binding_table_pool);
PRINT_HEAP(internal_surface_state_pool);
PRINT_HEAP(scratch_surface_state_pool);
@@ -61,8 +59,8 @@ anv_device_print_vas(struct anv_physical_device *device)
PRINT_HEAP(indirect_descriptor_pool);
PRINT_HEAP(indirect_push_descriptor_pool);
PRINT_HEAP(instruction_state_pool);
PRINT_HEAP(dynamic_state_db_pool);
PRINT_HEAP(descriptor_buffer_pool);
PRINT_HEAP(dynamic_state_pool);
PRINT_HEAP(dynamic_visible_pool);
PRINT_HEAP(push_descriptor_buffer_pool);
PRINT_HEAP(high_heap);
PRINT_HEAP(trtt);
@@ -120,14 +118,6 @@ anv_physical_device_init_va_ranges(struct anv_physical_device *device)
8 * _1Mb);
address = va_add(&device->va.bindless_surface_state_pool, address, 2 * _1Gb);
/* PRMs & simulation disagrees on the actual size of this heap. Take the
* smallest (simulation) so that it works everywhere.
*/
address = align64(address, _4Gb);
address = va_add(&device->va.dynamic_state_pool, address, _1Gb);
address = va_add(&device->va.sampler_state_pool, address, 2 * _1Gb);
if (device->indirect_descriptors) {
/* With indirect descriptors, descriptor buffers can go anywhere, they
* just need to be in a 4Gb aligned range, so all shader accesses can
@@ -147,15 +137,13 @@ anv_physical_device_init_va_ranges(struct anv_physical_device *device)
address = va_add(&device->va.instruction_state_pool, address, 2 * _1Gb);
address += 1 * _1Gb;
address = va_add(&device->va.dynamic_state_db_pool, address, _1Gb);
address = va_add(&device->va.descriptor_buffer_pool, address, 2 *_1Gb);
assert(device->va.descriptor_buffer_pool.addr % _4Gb == 0);
address = va_add(&device->va.dynamic_state_pool, address, _1Gb);
address = va_add(&device->va.dynamic_visible_pool, address,
device->info.verx10 >= 125 ? (2 * _1Gb) : (3 * _1Gb - 4096));
assert(device->va.dynamic_visible_pool.addr % _4Gb == 0);
if (device->info.verx10 >= 125)
address = va_add(&device->va.push_descriptor_buffer_pool, address, _1Gb - 4096);
assert(device->va.descriptor_buffer_pool.addr ==
align64(device->va.descriptor_buffer_pool.addr, 4 * _1Gb));
address = align64(address, device->info.mem_alignment);
address = va_add(&device->va.aux_tt_pool, address, 2 * _1Gb);

5
src/intel/vulkan/genX_blorp_exec.c
View File

@@ -121,10 +121,7 @@ blorp_get_dynamic_state(struct blorp_batch *batch,
enum blorp_dynamic_state name)
{
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
return (cmd_buffer->state.current_db_mode ==
ANV_CMD_DESCRIPTOR_BUFFER_MODE_BUFFER) ?
cmd_buffer->device->blorp.dynamic_states[name].db_state.offset :
cmd_buffer->device->blorp.dynamic_states[name].state.offset;
return cmd_buffer->device->blorp.dynamic_states[name].offset;
}
static void *

103
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -155,24 +155,24 @@ fill_state_base_addr(struct anv_cmd_buffer *cmd_buffer,
sba->BindlessSamplerStateBaseAddressModifyEnable = true;
#endif
if (cmd_buffer->state.pending_db_mode == ANV_CMD_DESCRIPTOR_BUFFER_MODE_BUFFER) {
sba->DynamicStateBaseAddress = (struct anv_address) {
.offset = device->physical->va.dynamic_state_db_pool.addr,
};
sba->DynamicStateBufferSize =
(device->physical->va.dynamic_state_db_pool.size +
device->physical->va.descriptor_buffer_pool.size +
device->physical->va.push_descriptor_buffer_pool.size) / 4096;
sba->DynamicStateMOCS = mocs;
sba->DynamicStateBaseAddressModifyEnable = true;
sba->DynamicStateBufferSizeModifyEnable = true;
sba->DynamicStateBaseAddress = (struct anv_address) {
.offset = device->physical->va.dynamic_state_pool.addr,
};
sba->DynamicStateBufferSize =
(device->physical->va.dynamic_state_pool.size +
device->physical->va.dynamic_visible_pool.size +
device->physical->va.push_descriptor_buffer_pool.size) / 4096;
sba->DynamicStateMOCS = mocs;
sba->DynamicStateBaseAddressModifyEnable = true;
sba->DynamicStateBufferSizeModifyEnable = true;
if (cmd_buffer->state.pending_db_mode == ANV_CMD_DESCRIPTOR_BUFFER_MODE_BUFFER) {
#if GFX_VERx10 >= 125
sba->BindlessSurfaceStateBaseAddress = (struct anv_address) {
.offset = device->physical->va.descriptor_buffer_pool.addr,
.offset = device->physical->va.dynamic_visible_pool.addr,
};
sba->BindlessSurfaceStateSize =
(device->physical->va.descriptor_buffer_pool.size +
(device->physical->va.dynamic_visible_pool.size +
device->physical->va.push_descriptor_buffer_pool.size) - 1;
sba->BindlessSurfaceStateMOCS = mocs;
sba->BindlessSurfaceStateBaseAddressModifyEnable = true;
@@ -183,9 +183,9 @@ fill_state_base_addr(struct anv_cmd_buffer *cmd_buffer,
anv_address_physical(device->workaround_address);
const uint64_t surfaces_size =
cmd_buffer->state.descriptor_buffers.surfaces_address != 0 ?
MIN2(device->physical->va.descriptor_buffer_pool.size -
MIN2(device->physical->va.dynamic_visible_pool.size -
(cmd_buffer->state.descriptor_buffers.surfaces_address -
device->physical->va.descriptor_buffer_pool.addr),
device->physical->va.dynamic_visible_pool.addr),
anv_physical_device_bindless_heap_size(device->physical, true)) :
(device->workaround_bo->size - device->workaround_address.offset);
sba->BindlessSurfaceStateBaseAddress = (struct anv_address) {
@@ -197,16 +197,6 @@ fill_state_base_addr(struct anv_cmd_buffer *cmd_buffer,
#endif /* GFX_VERx10 < 125 */
} else if (!device->physical->indirect_descriptors) {
#if GFX_VERx10 >= 125
sba->DynamicStateBaseAddress = (struct anv_address) {
.offset = device->physical->va.dynamic_state_pool.addr,
};
sba->DynamicStateBufferSize =
(device->physical->va.dynamic_state_pool.size +
device->physical->va.sampler_state_pool.size) / 4096;
sba->DynamicStateMOCS = mocs;
sba->DynamicStateBaseAddressModifyEnable = true;
sba->DynamicStateBufferSizeModifyEnable = true;
sba->BindlessSurfaceStateBaseAddress = (struct anv_address) {
.offset = device->physical->va.internal_surface_state_pool.addr,
};
@@ -219,16 +209,6 @@ fill_state_base_addr(struct anv_cmd_buffer *cmd_buffer,
unreachable("Direct descriptor not supported");
#endif
} else {
sba->DynamicStateBaseAddress = (struct anv_address) {
.offset = device->physical->va.dynamic_state_pool.addr,
};
sba->DynamicStateBufferSize =
(device->physical->va.dynamic_state_pool.size +
device->physical->va.sampler_state_pool.size) / 4096;
sba->DynamicStateMOCS = mocs;
sba->DynamicStateBaseAddressModifyEnable = true;
sba->DynamicStateBufferSizeModifyEnable = true;
sba->BindlessSurfaceStateBaseAddress =
(struct anv_address) { .offset =
device->physical->va.bindless_surface_state_pool.addr,
@@ -299,11 +279,8 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
_sba = sba;
}
bool db_mode_changed = false;
if (cmd_buffer->state.current_db_mode != cmd_buffer->state.pending_db_mode) {
if (cmd_buffer->state.current_db_mode != cmd_buffer->state.pending_db_mode)
cmd_buffer->state.current_db_mode = cmd_buffer->state.pending_db_mode;
db_mode_changed = true;
}
#if INTEL_NEEDS_WA_1607854226
/* Wa_1607854226:
@@ -382,40 +359,6 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
assert(cmd_buffer->state.current_db_mode !=
ANV_CMD_DESCRIPTOR_BUFFER_MODE_UNKNOWN);
if (db_mode_changed) {
#if GFX_VER == 11 || GFX_VER == 125
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
ptr.SliceHashStatePointerValid = true;
ptr.SliceHashTableStatePointer = cmd_buffer->state.current_db_mode ==
ANV_CMD_DESCRIPTOR_BUFFER_MODE_BUFFER ?
device->slice_hash_db.offset :
device->slice_hash.offset;
}
#endif
/* Changing the dynamic state location affects all the states having
* offset relative to that pointer.
*/
struct anv_gfx_dynamic_state *hw_state = &cmd_buffer->state.gfx.dyn_state;
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_SF_CLIP);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SCISSOR);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_CC_STATE);
BITSET_SET(hw_state->dirty, ANV_GFX_STATE_BLEND_STATE);
if (device->vk.enabled_extensions.KHR_fragment_shading_rate) {
struct vk_dynamic_graphics_state *dyn =
&cmd_buffer->vk.dynamic_graphics_state;
BITSET_SET(dyn->dirty, MESA_VK_DYNAMIC_FSR);
}
#if GFX_VERx10 < 125
/* The push constant data for compute shader is an offset in the dynamic
* state heap. If we change it, we need to reemit the push constants.
*/
cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
cmd_buffer->state.compute.base.push_constants_data_dirty = true;
#endif
}
#if GFX_VERx10 >= 125
assert(sba.BindlessSurfaceStateBaseAddress.offset != 0);
@@ -2349,11 +2292,7 @@ emit_samplers(struct anv_cmd_buffer *cmd_buffer,
if (sampler == NULL)
continue;
memcpy(state->map + (s * 16),
cmd_buffer->state.current_db_mode ==
ANV_CMD_DESCRIPTOR_BUFFER_MODE_BUFFER ?
sampler->db_state[binding->plane] :
sampler->state[binding->plane],
memcpy(state->map + (s * 16), sampler->state[binding->plane],
sizeof(sampler->state[0]));
}
@@ -2707,7 +2646,7 @@ update_descriptor_set_surface_state(struct anv_cmd_buffer *cmd_buffer,
&device->va.push_descriptor_buffer_pool :
&device->va.internal_surface_state_pool;
const struct anv_va_range *va_range =
buffer_index == -1 ? push_va_range : &device->va.descriptor_buffer_pool;
buffer_index == -1 ? push_va_range : &device->va.dynamic_visible_pool;
const uint64_t descriptor_set_addr =
(buffer_index == -1 ? va_range->addr :
cmd_buffer->state.descriptor_buffers.address[buffer_index]) +
@@ -2750,7 +2689,7 @@ compute_descriptor_set_surface_offset(const struct anv_cmd_buffer *cmd_buffer,
device->va.push_descriptor_buffer_pool.addr :
cmd_buffer->state.descriptor_buffers.address[buffer_index];
return (buffer_address - device->va.descriptor_buffer_pool.addr) +
return (buffer_address - device->va.dynamic_visible_pool.addr) +
pipe_state->descriptor_buffers[set_idx].buffer_offset;
}
@@ -2770,7 +2709,7 @@ compute_descriptor_set_sampler_offset(const struct anv_cmd_buffer *cmd_buffer,
device->va.push_descriptor_buffer_pool.addr :
cmd_buffer->state.descriptor_buffers.address[buffer_index];
return (buffer_address - device->va.dynamic_state_db_pool.addr) +
return (buffer_address - device->va.dynamic_state_pool.addr) +
pipe_state->descriptor_buffers[set_idx].buffer_offset;
}
@@ -2812,7 +2751,7 @@ genX(flush_descriptor_buffers)(struct anv_cmd_buffer *cmd_buffer,
struct anv_device *device = cmd_buffer->device;
push_constants->surfaces_base_offset =
(cmd_buffer->state.descriptor_buffers.surfaces_address -
device->physical->va.descriptor_buffer_pool.addr);
device->physical->va.dynamic_visible_pool.addr);
#endif
cmd_buffer->state.push_constants_dirty |=

17
src/intel/vulkan/genX_gfx_state.c
View File

@@ -99,14 +99,8 @@ get_cps_state_offset(struct anv_cmd_buffer *cmd_buffer, bool cps_enabled,
{
struct anv_device *device = cmd_buffer->device;
if (!cps_enabled) {
assert(cmd_buffer->state.current_db_mode !=
ANV_CMD_DESCRIPTOR_BUFFER_MODE_UNKNOWN);
return cmd_buffer->state.current_db_mode ==
ANV_CMD_DESCRIPTOR_BUFFER_MODE_BUFFER ?
device->cps_states_db.offset :
device->cps_states.offset;
}
if (!cps_enabled)
return device->cps_states.offset;
uint32_t offset;
static const uint32_t size_index[] = {
@@ -131,12 +125,7 @@ get_cps_state_offset(struct anv_cmd_buffer *cmd_buffer, bool cps_enabled,
offset *= MAX_VIEWPORTS * GENX(CPS_STATE_length) * 4;
assert(cmd_buffer->state.current_db_mode !=
ANV_CMD_DESCRIPTOR_BUFFER_MODE_UNKNOWN);
return (cmd_buffer->state.current_db_mode ==
ANV_CMD_DESCRIPTOR_BUFFER_MODE_BUFFER ?
device->cps_states_db.offset :
device->cps_states.offset) + offset;
return device->cps_states.offset + offset;
}
#endif /* GFX_VER >= 12 */

71
src/intel/vulkan/genX_init_state.c
View File

@@ -256,7 +256,7 @@ init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
device->physical->va.dynamic_state_pool.addr,
};
sba.DynamicStateBufferSize = (device->physical->va.dynamic_state_pool.size +
device->physical->va.sampler_state_pool.size) / 4096;
device->physical->va.dynamic_visible_pool.size) / 4096;
sba.DynamicStateMOCS = mocs;
sba.DynamicStateBaseAddressModifyEnable = true;
sba.DynamicStateBufferSizeModifyEnable = true;
@@ -906,17 +906,6 @@ genX(init_device_state)(struct anv_device *device)
return res;
}
if (device->vk.enabled_extensions.EXT_descriptor_buffer &&
device->slice_hash.alloc_size) {
device->slice_hash_db =
anv_state_pool_alloc(&device->dynamic_state_db_pool,
device->slice_hash.alloc_size, 64);
memcpy(device->slice_hash_db.map,
device->slice_hash.map,
device->slice_hash.alloc_size);
}
return res;
}
@@ -1199,21 +1188,35 @@ VkResult genX(CreateSampler)(
sampler->n_planes = ycbcr_info ? ycbcr_info->n_planes : 1;
uint32_t border_color_stride = 64;
uint32_t border_color_offset, border_color_db_offset = 0;
uint32_t border_color_offset;
void *border_color_ptr;
if (sampler->vk.border_color <= VK_BORDER_COLOR_INT_OPAQUE_WHITE) {
border_color_offset = device->border_colors.offset +
pCreateInfo->borderColor *
border_color_stride;
border_color_db_offset = device->border_colors_db.offset +
pCreateInfo->borderColor *
border_color_stride;
border_color_ptr = device->border_colors.map +
pCreateInfo->borderColor * border_color_stride;
} else {
assert(vk_border_color_is_custom(sampler->vk.border_color));
sampler->custom_border_color =
anv_state_reserved_array_pool_alloc(&device->custom_border_colors, false);
if (pCreateInfo->flags & VK_SAMPLER_CREATE_DESCRIPTOR_BUFFER_CAPTURE_REPLAY_BIT_EXT) {
const VkOpaqueCaptureDescriptorDataCreateInfoEXT *opaque_info =
vk_find_struct_const(pCreateInfo->pNext,
OPAQUE_CAPTURE_DESCRIPTOR_DATA_CREATE_INFO_EXT);
if (opaque_info) {
uint32_t alloc_idx = *((const uint32_t *)opaque_info->opaqueCaptureDescriptorData);
sampler->custom_border_color =
anv_state_reserved_array_pool_alloc_index(&device->custom_border_colors, alloc_idx);
} else {
sampler->custom_border_color =
anv_state_reserved_array_pool_alloc(&device->custom_border_colors, true);
}
} else {
sampler->custom_border_color =
anv_state_reserved_array_pool_alloc(&device->custom_border_colors, false);
}
if (sampler->custom_border_color.alloc_size == 0)
return vk_error(device, VK_ERROR_OUT_OF_DEVICE_MEMORY);
border_color_offset = sampler->custom_border_color.offset;
border_color_ptr = sampler->custom_border_color.map;
@@ -1237,29 +1240,6 @@ VkResult genX(CreateSampler)(
}
memcpy(border_color_ptr, color.u32, sizeof(color));
if (device->vk.enabled_extensions.EXT_descriptor_buffer) {
if (pCreateInfo->flags & VK_SAMPLER_CREATE_DESCRIPTOR_BUFFER_CAPTURE_REPLAY_BIT_EXT) {
const VkOpaqueCaptureDescriptorDataCreateInfoEXT *opaque_info =
vk_find_struct_const(pCreateInfo->pNext,
OPAQUE_CAPTURE_DESCRIPTOR_DATA_CREATE_INFO_EXT);
if (opaque_info) {
uint32_t alloc_idx = *((const uint32_t *)opaque_info->opaqueCaptureDescriptorData);
sampler->custom_border_color_db =
anv_state_reserved_array_pool_alloc_index(&device->custom_border_colors_db, alloc_idx);
} else {
sampler->custom_border_color_db =
anv_state_reserved_array_pool_alloc(&device->custom_border_colors_db, true);
}
} else {
sampler->custom_border_color_db =
anv_state_reserved_array_pool_alloc(&device->custom_border_colors_db, false);
}
if (sampler->custom_border_color_db.alloc_size == 0)
return vk_error(device, VK_ERROR_OUT_OF_DEVICE_MEMORY);
border_color_db_offset = sampler->custom_border_color_db.offset;
memcpy(sampler->custom_border_color_db.map, color.u32, sizeof(color));
}
}
const bool seamless_cube =
@@ -1357,11 +1337,6 @@ VkResult genX(CreateSampler)(
*/
sampler_state.BorderColorPointer = border_color_offset;
GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
if (device->vk.enabled_extensions.EXT_descriptor_buffer) {
sampler_state.BorderColorPointer = border_color_db_offset;
GENX(SAMPLER_STATE_pack)(NULL, sampler->db_state[p], &sampler_state);
}
}
/* If we have bindless, allocate enough samplers. We allocate 32 bytes
@@ -1397,14 +1372,14 @@ genX(emit_embedded_sampler)(struct anv_device *device,
memcpy(&sampler->key, &binding->key, sizeof(binding->key));
sampler->border_color_state =
anv_state_pool_alloc(&device->dynamic_state_db_pool,
anv_state_pool_alloc(&device->dynamic_state_pool,
sizeof(struct gfx8_border_color), 64);
memcpy(sampler->border_color_state.map,
binding->key.color,
sizeof(binding->key.color));
sampler->sampler_state =
anv_state_pool_alloc(&device->dynamic_state_db_pool,
anv_state_pool_alloc(&device->dynamic_state_pool,
ANV_SAMPLER_STATE_SIZE, 32);
struct GENX(SAMPLER_STATE) sampler_state = {

6
src/intel/vulkan/i915/anv_batch_chain.c
View File

@@ -411,12 +411,6 @@ setup_execbuf_for_cmd_buffers(struct anv_execbuf *execbuf,
if (result != VK_SUCCESS)
return result;
if (device->vk.enabled_extensions.EXT_descriptor_buffer) {
result = pin_state_pool(device, execbuf, &device->dynamic_state_db_pool);
if (result != VK_SUCCESS)
return result;
}
result = pin_state_pool(device, execbuf, &device->general_state_pool);
if (result != VK_SUCCESS)
return result;