brw/vec4: Don't convert tex dest type to glsl_type
We were using nir_tex_instr::dest_type to a glsl_type, then passing it to emit_texture(), only to just check the number of components. Just pass the number of components directly. This lets us delete brw_glsl_base_type_for_nir_type, which was asserting with nir_texop_all_samples_equal because it didn't handle bool32. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7989>
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@@ -1482,42 +1482,6 @@ brw_type_for_nir_type(const struct gen_device_info *devinfo, nir_alu_type type)
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return BRW_REGISTER_TYPE_F;
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}
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/* Returns the glsl_base_type corresponding to a nir_alu_type.
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* This is used by both brw_vec4_nir and brw_fs_nir.
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*/
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enum glsl_base_type
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brw_glsl_base_type_for_nir_type(nir_alu_type type)
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{
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switch (type) {
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case nir_type_float:
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case nir_type_float32:
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return GLSL_TYPE_FLOAT;
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case nir_type_float16:
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return GLSL_TYPE_FLOAT16;
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case nir_type_float64:
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return GLSL_TYPE_DOUBLE;
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case nir_type_int:
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case nir_type_int32:
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return GLSL_TYPE_INT;
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case nir_type_uint:
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case nir_type_uint32:
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return GLSL_TYPE_UINT;
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case nir_type_int16:
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return GLSL_TYPE_INT16;
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case nir_type_uint16:
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return GLSL_TYPE_UINT16;
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default:
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unreachable("bad type");
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}
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}
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nir_shader *
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brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler,
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const nir_shader_compiler_options *options,
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@@ -156,8 +156,6 @@ uint32_t brw_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic);
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enum brw_reg_type brw_type_for_nir_type(const struct gen_device_info *devinfo,
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nir_alu_type type);
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enum glsl_base_type brw_glsl_base_type_for_nir_type(nir_alu_type type);
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void brw_nir_setup_glsl_uniforms(void *mem_ctx, nir_shader *shader,
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const struct gl_program *prog,
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struct brw_stage_prog_data *stage_prog_data,
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@@ -254,7 +254,7 @@ public:
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void emit_texture(ir_texture_opcode op,
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dst_reg dest,
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const glsl_type *dest_type,
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int dest_components,
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src_reg coordinate,
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int coord_components,
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src_reg shadow_comparator,
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@@ -1950,14 +1950,6 @@ ir_texture_opcode_for_nir_texop(nir_texop texop)
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return op;
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}
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static const glsl_type *
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glsl_type_for_nir_alu_type(nir_alu_type alu_type,
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unsigned components)
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{
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return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type),
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components, 1);
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}
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void
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vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
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{
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@@ -1973,9 +1965,6 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
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src_reg sample_index;
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src_reg mcs;
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const glsl_type *dest_type =
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glsl_type_for_nir_alu_type(instr->dest_type,
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nir_tex_instr_dest_size(instr));
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dst_reg dest = get_nir_dest(instr->dest, instr->dest_type);
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/* The hardware requires a LOD for buffer textures */
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@@ -2102,7 +2091,8 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
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ir_texture_opcode op = ir_texture_opcode_for_nir_texop(instr->op);
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emit_texture(op, dest, dest_type, coordinate, instr->coord_components,
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emit_texture(op, dest, nir_tex_instr_dest_size(instr),
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coordinate, instr->coord_components,
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shadow_comparator,
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lod, lod2, sample_index,
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constant_offset, offset_value, mcs,
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@@ -827,7 +827,7 @@ vec4_visitor::is_high_sampler(src_reg sampler)
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void
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vec4_visitor::emit_texture(ir_texture_opcode op,
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dst_reg dest,
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const glsl_type *dest_type,
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int dest_components,
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src_reg coordinate,
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int coord_components,
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src_reg shadow_comparator,
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@@ -964,7 +964,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
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emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_YW), lod2));
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inst->mlen++;
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if (dest_type->vector_elements == 3 || shadow_comparator.file != BAD_FILE) {
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if (dest_components == 3 || shadow_comparator.file != BAD_FILE) {
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lod.swizzle = BRW_SWIZZLE_ZZZZ;
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lod2.swizzle = BRW_SWIZZLE_ZZZZ;
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emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_X), lod));
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