pan/va: Add disassembler generator
When we bring up the Valhall compiler in Mesa, we will like to have a disassembler in native code, so we shouldn't write our disassembler in Python. Instead, we write a disassembler generator in Python with mako templates, which will produce a va_disasm_instr entrypoint from the architecture defined in ISA.xml and valhall.py. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
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Alyssa Rosenzweig
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Marge Bot
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227547db48
commit
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244
src/panfrost/bifrost/valhall/disasm.py
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244
src/panfrost/bifrost/valhall/disasm.py
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from valhall import instructions, immediates, enums, typesize, safe_name
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from mako.template import Template
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from mako import exceptions
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template = """
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#include "disassemble.h"
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% for name, en in ENUMS.items():
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UNUSED static const char *valhall_${name}[] = {
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% for v in en.values:
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"${"" if v.default else "." + v.value}",
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% endfor
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};
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% endfor
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static const uint32_t va_immediates[32] = {
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% for imm in IMMEDIATES:
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${hex(imm)},
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% endfor
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};
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/* Byte 7 has instruction metadata, analogous to Bifrost's clause header */
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struct va_metadata {
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bool opcode_high : 1;
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unsigned immediate_mode : 2;
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unsigned action : 3;
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bool do_action : 1;
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bool unk3 : 1;
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} __attribute__((packed));
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static inline void
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va_print_metadata(FILE *fp, uint8_t meta)
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{
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struct va_metadata m;
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memcpy(&m, &meta, 1);
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fputs(valhall_immediate_mode[m.immediate_mode], fp);
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if (m.do_action) {
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fputs(valhall_action[m.action], fp);
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} else if (m.action) {
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fprintf(fp, ".wait%s%s%s",
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m.action & (1 << 0) ? "0" : "",
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m.action & (1 << 1) ? "1" : "",
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m.action & (1 << 2) ? "2" : "");
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}
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if (m.unk3)
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fprintf(fp, ".unk3");
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}
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static inline void
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va_print_src(FILE *fp, uint8_t src, unsigned imm_mode)
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{
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unsigned type = (src >> 6);
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unsigned value = (src & 0x3F);
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if (type == VA_SRC_IMM_TYPE) {
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if (value >= 32) {
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if (imm_mode == 0) {
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if (value >= 0x30)
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fprintf(fp, "blend_descriptor_%u_%c", (value - 0x30) >> 1, value & 1 ? 'y' : 'x');
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else if (value == 0x2A)
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fprintf(fp, "atest_datum");
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else
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fprintf(fp, "unk:%X", value);
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} else if (imm_mode == 1) {
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if (value < 0x28)
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fputs(valhall_thread_storage_pointers[value - 0x20] + 1, fp);
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else
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fprintf(fp, "unk:%X", value);
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} else if (imm_mode == 3) {
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if (value < 0x40)
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fputs(valhall_thread_identification[value - 0x20] + 1, fp);
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else
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fprintf(fp, "unk:%X", value);
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} else {
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fprintf(fp, "unk:%X", value);
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}
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} else {
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fprintf(fp, "0x%X", va_immediates[value]);
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}
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} else if (type == VA_SRC_UNIFORM_TYPE) {
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fprintf(fp, "u%u", value);
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} else {
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bool discard = (type & 1);
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fprintf(fp, "%sr%u", discard ? "`" : "", value);
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}
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}
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static inline void
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va_print_float_src(FILE *fp, uint8_t src, unsigned imm_mode, bool neg, bool abs)
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{
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unsigned type = (src >> 6);
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unsigned value = (src & 0x3F);
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if (type == VA_SRC_IMM_TYPE) {
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assert(value < 32 && "overflow in LUT");
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fprintf(fp, "0x%X", va_immediates[value]);
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} else {
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va_print_src(fp, src, imm_mode);
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}
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if (neg)
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fprintf(fp, ".neg");
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if (abs)
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fprintf(fp, ".abs");
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}
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void
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va_disasm_instr(FILE *fp, uint64_t instr)
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{
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unsigned primary_opc = (instr >> 48) & MASK(9);
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unsigned imm_mode = (instr >> 57) & MASK(2);
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unsigned secondary_opc = 0;
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switch (primary_opc) {
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% for bucket in OPCODES:
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<%
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ops = OPCODES[bucket]
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ambiguous = (len(ops) > 1)
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%>
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% if len(ops) > 0:
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case ${hex(bucket)}:
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% if ambiguous:
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secondary_opc = (instr >> ${ops[0].secondary_shift}) & ${hex(ops[0].secondary_mask)};
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% endif
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% for op in ops:
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<% no_comma = True %>
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% if ambiguous:
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if (secondary_opc == ${op.opcode2}) {
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% endif
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fputs("${op.name}", fp);
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% for mod in op.modifiers:
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% if mod.name not in ["left", "staging_register_count"]:
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% if mod.size == 1:
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if (instr & BIT(${mod.start})) fputs(".${mod.name}", fp);
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% else:
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fputs(valhall_${safe_name(mod.name)}[(instr >> ${mod.start}) & ${hex((1 << mod.size) - 1)}], fp);
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% endif
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% endif
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% endfor
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va_print_metadata(fp, instr >> 56);
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fputs(" ", fp);
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% if len(op.dests) > 0:
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<% no_comma = False %>
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va_print_dest(fp, (instr >> 40), true);
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% endif
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% for index, sr in enumerate(op.staging):
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% if not no_comma:
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fputs(", ", fp);
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% endif
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<%
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no_comma = False
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sr_count = "((instr >> 33) & MASK(3))" if sr.count == 0 else sr.count
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%>
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// assert(((instr >> ${sr.start}) & 0xC0) == ${sr.encoded_flags});
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for (unsigned i = 0; i < ${sr_count}; ++i) {
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fprintf(fp, "%sr%u", (i == 0) ? "@" : ":",
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(uint32_t) (((instr >> ${sr.start}) & 0x3F) + i));
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}
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% endfor
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% for i, src in enumerate(op.srcs):
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% if not no_comma:
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fputs(", ", fp);
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% endif
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<% no_comma = False %>
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% if src.absneg:
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va_print_float_src(fp, instr >> ${8 * i}, imm_mode,
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instr & BIT(${src.offset['neg']}),
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instr & BIT(${src.offset['abs']}));
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% elif src.is_float:
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va_print_float_src(fp, instr >> ${8 * i}, imm_mode, false, false);
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% else:
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va_print_src(fp, instr >> ${8 * i}, imm_mode);
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% endif
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% if src.swizzle:
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% if src.size == 32:
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fputs(valhall_widen[(instr >> ${src.offset['swizzle']}) & 3], fp);
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% else:
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fputs(valhall_swizzles_16_bit[(instr >> ${src.offset['swizzle']}) & 3], fp);
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% endif
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% endif
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% if src.lanes:
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fputs(valhall_lanes_8_bit[(instr >> ${src.offset['widen']}) & 0xF], fp);
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% elif src.widen:
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fputs(valhall_swizzles_${src.size}_bit[(instr >> ${src.offset['widen']}) & 0xF], fp);
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% endif
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% if src.lane:
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fputs(valhall_lane_${src.size}_bit[(instr >> ${src.lane}) & 0x3], fp);
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% endif
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% if 'not' in src.offset:
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if (instr & BIT(${src.offset['not']})) fputs(".not", fp);
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% endif
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% endfor
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% for imm in op.immediates:
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<%
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prefix = "#" if imm.name == "constant" else imm.name + ":"
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fmt = "%d" if imm.signed else "0x%X"
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%>
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fprintf(fp, ", ${prefix}${fmt}", (uint32_t) ${"SEXT(" if imm.signed else ""}
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((instr >> ${imm.start}) & MASK(${imm.size})) ${f", {imm.size})" if imm.signed else ""});
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% endfor
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% if ambiguous:
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}
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% endif
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% endfor
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break;
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% endif
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% endfor
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}
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}
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"""
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# Bucket by opcode for hierarchical disassembly
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OPCODE_BUCKETS = {}
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for ins in instructions:
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opc = ins.opcode
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OPCODE_BUCKETS[opc] = OPCODE_BUCKETS.get(opc, []) + [ins]
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# Check that each bucket may be disambiguated
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for op in OPCODE_BUCKETS:
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bucket = OPCODE_BUCKETS[op]
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# Nothing to disambiguate
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if len(bucket) < 2:
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continue
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SECONDARY = {}
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for ins in bucket:
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# Number of sources determines opcode2 placement, must be consistent
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assert(len(ins.srcs) == len(bucket[0].srcs))
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# Must not repeat, else we're ambiguous
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assert(ins.opcode2 not in SECONDARY)
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SECONDARY[ins.opcode2] = ins
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try:
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print(Template(template).render(OPCODES = OPCODE_BUCKETS, IMMEDIATES = immediates, ENUMS = enums, typesize = typesize, safe_name = safe_name))
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except:
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print(exceptions.text_error_template().render())
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62
src/panfrost/bifrost/valhall/disassemble.h
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62
src/panfrost/bifrost/valhall/disassemble.h
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@@ -0,0 +1,62 @@
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#ifndef __DISASM_H
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#define __DISASM_H
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#include <stdio.h>
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#include <stdint.h>
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#include <inttypes.h>
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#include <assert.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <string.h>
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#define BIT(b) (1ull << (b))
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#define MASK(count) ((1ull << (count)) - 1)
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#define SEXT(b, count) ((b ^ BIT(count - 1)) - BIT(count - 1))
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#define UNUSED __attribute__((unused))
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static inline float fui(uint32_t u) { float f; memcpy(&f, &u, 4); return f; }
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#define VA_SRC_UNIFORM_TYPE 0x2
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#define VA_SRC_IMM_TYPE 0x3
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static inline void
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va_print_dest(FILE *fp, uint8_t dest, bool can_mask)
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{
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unsigned mask = (dest >> 6);
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unsigned value = (dest & 0x3F);
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fprintf(fp, "r%u", value);
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/* Should write at least one component */
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// assert(mask != 0);
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// assert(mask == 0x3 || can_mask);
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if (mask != 0x3)
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fprintf(fp, ".h%u", (mask == 1) ? 0 : 1);
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}
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void va_disasm_instr(FILE *fp, uint64_t instr);
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static inline void
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disassemble_valhall(FILE *fp, const uint64_t *code, unsigned size)
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{
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assert((size & 7) == 0);
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/* Segment into 8-byte instructions */
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for (unsigned i = 0; i < (size / 8); ++i) {
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uint64_t instr = code[i];
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/* TODO: is there a stop-bit? or does all-0's mean stop? */
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if (instr == 0)
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return;
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/* Print byte pattern */
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for (unsigned j = 0; j < 8; ++j)
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fprintf(fp, "%02x ", (uint8_t) (instr >> (j * 8)));
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fprintf(fp, " ");
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va_disasm_instr(fp, instr);
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fprintf(fp, "\n");
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}
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}
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#endif
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