From 67b778445afec51883e36618c8d5c535b3fd149f Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Fri, 5 Jul 2024 18:59:30 +0300 Subject: [PATCH] brw: fix uniform rebuild of sources If you have something like this : con 32 %66 = @load_reg (%62) (base=0, legacy_fabs=0, legacy_fneg=0) con 32 %27 = @resource_intel (%22 (0xdeaddead), %66, %67, %17 (0x0)) (desc_set=2, binding=96, resource_intel=0, resource_block_intel=-1) Just copying the brw_reg in ssa_values[] is not enough for the load_reg intrinsic. We need to call get_nir_src() to force some logic to create the register correct. Signed-off-by: Lionel Landwerlin Fixes: b8209d69ff ("intel/fs: Add support for new-style registers") Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 0f4042931f5..f423f4ccd00 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -6032,7 +6032,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, try_rebuild_source(ntb, bld, instr->src[1].ssa); } ntb.ssa_values[instr->def.index] = - ntb.ssa_values[instr->src[1].ssa->index]; + get_nir_src(ntb, instr->src[1]); break; case nir_intrinsic_load_reg: