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radv: zero-initialize radv_shader_args right before declaring them

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This should allow us to remove a big memset when compiling a
graphics pipeline. This is mostly for imported NIR stages which
don't go through radv_pipeline_stage_init().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20947>
This commit is contained in:
Samuel Pitoiset
2023-03-09 15:04:29 +01:00
parent c505f892d4
commit 67635bb3e3
5 changed files with 41 additions and 32 deletions
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24
src/amd/vulkan/radv_pipeline.c
View File

@@ -2558,15 +2558,8 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
{
enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
radv_foreach_stage(i, active_nir_stages) {
stages[i].args.is_gs_copy_shader = false;
stages[i].args.explicit_scratch_args = !radv_use_llvm_for_stage(device, i);
stages[i].args.remap_spi_ps_input = !radv_use_llvm_for_stage(device, i);
stages[i].args.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
}
if (gfx_level >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) {
radv_declare_shader_args(gfx_level, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info,
radv_declare_shader_args(device, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info,
MESA_SHADER_TESS_CTRL, true, MESA_SHADER_VERTEX,
&stages[MESA_SHADER_TESS_CTRL].args);
stages[MESA_SHADER_TESS_CTRL].info.user_sgprs_locs = stages[MESA_SHADER_TESS_CTRL].args.user_sgprs_locs;
@@ -2584,7 +2577,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
if (gfx_level >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) {
gl_shader_stage pre_stage =
stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
radv_declare_shader_args(gfx_level, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info,
radv_declare_shader_args(device, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info,
MESA_SHADER_GEOMETRY, true, pre_stage,
&stages[MESA_SHADER_GEOMETRY].args);
stages[MESA_SHADER_GEOMETRY].info.user_sgprs_locs = stages[MESA_SHADER_GEOMETRY].args.user_sgprs_locs;
@@ -2599,8 +2592,8 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
}
u_foreach_bit(i, active_nir_stages) {
radv_declare_shader_args(gfx_level, pipeline_key, &stages[i].info, i, false,
MESA_SHADER_VERTEX, &stages[i].args);
radv_declare_shader_args(device, pipeline_key, &stages[i].info, i, false, MESA_SHADER_VERTEX,
&stages[i].args);
stages[i].info.user_sgprs_locs = stages[i].args.user_sgprs_locs;
stages[i].info.inline_push_constant_mask = stages[i].args.ac.inline_push_const_mask;
}
@@ -2984,11 +2977,11 @@ radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
info.outinfo = gs_info->outinfo;
info.force_vrs_per_vertex = gs_info->force_vrs_per_vertex;
struct radv_shader_args gs_copy_args = {0};
struct radv_shader_args gs_copy_args;
gs_copy_args.is_gs_copy_shader = true;
gs_copy_args.explicit_scratch_args = !radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX);
radv_declare_shader_args(device->physical_device->rad_info.gfx_level, pipeline_key, &info,
MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX, &gs_copy_args);
radv_declare_shader_args(device, pipeline_key, &info, MESA_SHADER_VERTEX, false,
MESA_SHADER_VERTEX, &gs_copy_args);
info.user_sgprs_locs = gs_copy_args.user_sgprs_locs;
info.inline_push_constant_mask = gs_copy_args.ac.inline_push_const_mask;
@@ -5440,8 +5433,7 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline *pipeline,
cs_stage.args.explicit_scratch_args = !radv_use_llvm_for_stage(device, MESA_SHADER_COMPUTE);
cs_stage.args.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
radv_declare_shader_args(device->physical_device->rad_info.gfx_level, pipeline_key,
&cs_stage.info, MESA_SHADER_COMPUTE, false,
radv_declare_shader_args(device, pipeline_key, &cs_stage.info, MESA_SHADER_COMPUTE, false,
MESA_SHADER_VERTEX, &cs_stage.args);
cs_stage.info.user_sgprs_locs = cs_stage.args.user_sgprs_locs;

5
src/amd/vulkan/radv_pipeline_rt.c
View File

@@ -271,9 +271,8 @@ radv_rt_pipeline_compile(struct radv_pipeline *pipeline,
rt_stage.args.explicit_scratch_args = !radv_use_llvm_for_stage(device, rt_stage.stage);
rt_stage.args.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
radv_declare_shader_args(device->physical_device->rad_info.gfx_level, pipeline_key,
&rt_stage.info, rt_stage.stage, false, MESA_SHADER_NONE,
&rt_stage.args);
radv_declare_shader_args(device, pipeline_key, &rt_stage.info, rt_stage.stage, false,
MESA_SHADER_NONE, &rt_stage.args);
rt_stage.info.user_sgprs_locs = rt_stage.args.user_sgprs_locs;
rt_stage.info.inline_push_constant_mask = rt_stage.args.ac.inline_push_const_mask;

9
src/amd/vulkan/radv_shader.c
View File

@@ -2460,11 +2460,10 @@ radv_create_trap_handler_shader(struct radv_device *device)
info.wave_size = 64;
struct radv_shader_args args = {0};
struct radv_shader_args args;
args.explicit_scratch_args = true;
args.is_trap_handler_shader = true;
radv_declare_shader_args(device->physical_device->rad_info.gfx_level, &key, &info, stage, false,
MESA_SHADER_VERTEX, &args);
radv_declare_shader_args(device, &key, &info, stage, false, MESA_SHADER_VERTEX, &args);
shader =
shader_compile(device, &b.shader, 1, stage, &info, &args, &key, true, false, false, &binary);
@@ -2527,7 +2526,7 @@ radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_ke
struct radv_pipeline_key pipeline_key = {0};
args.explicit_scratch_args = true;
radv_declare_shader_args(options.gfx_level, &pipeline_key, &info, key->next_stage,
radv_declare_shader_args(device, &pipeline_key, &info, key->next_stage,
key->next_stage != MESA_SHADER_VERTEX, MESA_SHADER_VERTEX, &args);
info.user_sgprs_locs = args.user_sgprs_locs;
@@ -2596,7 +2595,7 @@ radv_create_ps_epilog(struct radv_device *device, const struct radv_ps_epilog_ke
info.wave_size = device->physical_device->ps_wave_size;
info.workgroup_size = 64;
radv_declare_ps_epilog_args(device->physical_device->rad_info.gfx_level, key, &args);
radv_declare_ps_epilog_args(device, key, &args);
#ifdef LLVM_AVAILABLE
if (options.dump_shader || options.record_ir)

30
src/amd/vulkan/radv_shader_args.c
View File

@@ -557,12 +557,29 @@ set_ms_input_locs(struct radv_shader_args *args, uint8_t *user_sgpr_idx)
set_loc_shader(args, AC_UD_TASK_RING_ENTRY, user_sgpr_idx, 1);
}
static void
radv_init_shader_args(const struct radv_device *device, gl_shader_stage stage,
struct radv_shader_args *args)
{
memset(args, 0, sizeof(*args));
args->explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
args->remap_spi_ps_input = !radv_use_llvm_for_stage(device, stage);
args->load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
for (int i = 0; i < MAX_SETS; i++)
args->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
for (int i = 0; i < AC_UD_MAX_UD; i++)
args->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
}
void
radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipeline_key *key,
radv_declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
const struct radv_shader_info *info, gl_shader_stage stage,
bool has_previous_stage, gl_shader_stage previous_stage,
struct radv_shader_args *args)
{
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
struct user_sgpr_info user_sgpr_info;
bool needs_view_index = info->uses_view_index;
bool has_ngg_query = info->has_ngg_prim_query || info->has_ngg_xfb_query ||
@@ -577,10 +594,7 @@ radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipelin
has_previous_stage = true;
}
for (int i = 0; i < MAX_SETS; i++)
args->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
for (int i = 0; i < AC_UD_MAX_UD; i++)
args->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
radv_init_shader_args(device, stage, args);
allocate_user_sgprs(gfx_level, info, args, stage, has_previous_stage, previous_stage,
needs_view_index, has_ngg_query, has_ngg_provoking_vtx, key, &user_sgpr_info);
@@ -970,9 +984,13 @@ radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipelin
}
void
radv_declare_ps_epilog_args(enum amd_gfx_level gfx_level, const struct radv_ps_epilog_key *key,
radv_declare_ps_epilog_args(const struct radv_device *device, const struct radv_ps_epilog_key *key,
struct radv_shader_args *args)
{
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
radv_init_shader_args(device, MESA_SHADER_FRAGMENT, args);
ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ac.ring_offsets);
if (gfx_level < GFX11)
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);

5
src/amd/vulkan/radv_shader_args.h
View File

@@ -93,12 +93,13 @@ radv_shader_args_from_ac(struct ac_shader_args *args)
struct radv_pipeline_key;
struct radv_shader_info;
void radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipeline_key *key,
void radv_declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key,
const struct radv_shader_info *info, gl_shader_stage stage,
bool has_previous_stage, gl_shader_stage previous_stage,
struct radv_shader_args *args);
void radv_declare_ps_epilog_args(enum amd_gfx_level gfx_level, const struct radv_ps_epilog_key *key,
void radv_declare_ps_epilog_args(const struct radv_device *device,
const struct radv_ps_epilog_key *key,
struct radv_shader_args *args);
#endif