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radv: set PS_ITER_SAMPLE(1) for sample shading during cmdbuf recording

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This shouldn't be configured in the pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22218>
This commit is contained in:
Samuel Pitoiset
2023-03-30 17:40:28 +02:00
committed by Marge Bot
parent b750fe4c6a
commit 66da73e863
2 changed files with 16 additions and 8 deletions
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16
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -2557,6 +2557,7 @@ radv_emit_rasterization_samples(struct radv_cmd_buffer *cmd_buffer)
{ {
const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device; const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device;
const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer); unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer);
const struct radv_rendering_state *render = &cmd_buffer->state.render; const struct radv_rendering_state *render = &cmd_buffer->state.render;
unsigned pa_sc_mode_cntl_1 = pipeline->pa_sc_mode_cntl_1; unsigned pa_sc_mode_cntl_1 = pipeline->pa_sc_mode_cntl_1;
@@ -2576,6 +2577,16 @@ radv_emit_rasterization_samples(struct radv_cmd_buffer *cmd_buffer)
} }
} }
if (pdevice->rad_info.gfx_level >= GFX10_3 &&
(cmd_buffer->state.ms.sample_shading_enable || ps->info.ps.reads_sample_mask_in)) {
/* Make sure sample shading is enabled even if only MSAA1x is used because the SAMPLE_ITER
* combiner is in passthrough mode if PS_ITER_SAMPLE is 0, and it uses the per-draw rate. The
* default VRS rate when sample shading is enabled is 1x1.
*/
if (!G_028A4C_PS_ITER_SAMPLE(pa_sc_mode_cntl_1))
pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(1);
}
if (pdevice->rad_info.gfx_level >= GFX11) { if (pdevice->rad_info.gfx_level >= GFX11) {
unsigned num_samples = render->max_samples; unsigned num_samples = render->max_samples;
unsigned max_allowed_tiles_in_wave = 0; unsigned max_allowed_tiles_in_wave = 0;
@@ -6408,6 +6419,7 @@ radv_bind_mesh_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_shad
static void static void
radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *ps) radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *ps)
{ {
const enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level;
const struct radv_shader *previous_ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]; const struct radv_shader *previous_ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
const float min_sample_shading = 1.0f; const float min_sample_shading = 1.0f;
@@ -6424,6 +6436,10 @@ radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_
if (previous_ps && previous_ps->info.ps.reads_fully_covered != ps->info.ps.reads_fully_covered) if (previous_ps && previous_ps->info.ps.reads_fully_covered != ps->info.ps.reads_fully_covered)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE; cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE;
if (gfx_level >= GFX10_3 &&
previous_ps && previous_ps->info.ps.reads_sample_mask_in != ps->info.ps.reads_sample_mask_in)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
if (cmd_buffer->state.ms.sample_shading_enable != ps->info.ps.uses_sample_shading || if (cmd_buffer->state.ms.sample_shading_enable != ps->info.ps.uses_sample_shading ||
cmd_buffer->state.ms.min_sample_shading != min_sample_shading) { cmd_buffer->state.ms.min_sample_shading != min_sample_shading) {
cmd_buffer->state.ms.sample_shading_enable = ps->info.ps.uses_sample_shading; cmd_buffer->state.ms.sample_shading_enable = ps->info.ps.uses_sample_shading;

8
src/amd/vulkan/radv_pipeline.c
View File

@@ -522,14 +522,6 @@ gfx103_pipeline_init_vrs_state(struct radv_graphics_pipeline *pipeline,
* 2x2 coarse shading isn't enough. * 2x2 coarse shading isn't enough.
*/ */
vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE); vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE);
/* Make sure sample shading is enabled even if only MSAA1x is
* used because the SAMPLE_ITER combiner is in passthrough
* mode if PS_ITER_SAMPLE is 0, and it uses the per-draw rate.
* The default VRS rate when sample shading is enabled is 1x1.
*/
if (!G_028A4C_PS_ITER_SAMPLE(pipeline->pa_sc_mode_cntl_1))
pipeline->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(1);
} else { } else {
vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_PASSTHRU); vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_PASSTHRU);
} }