iris: Skip resolves and flushes altogether if unnecessary
Improves drawoverhead baseline scores by 1.17x.
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@@ -125,12 +125,15 @@ enum iris_param_domain {
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#define IRIS_DIRTY_VF_SGVS (1ull << 52)
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#define IRIS_DIRTY_VF (1ull << 53)
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#define IRIS_DIRTY_VF_TOPOLOGY (1ull << 54)
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#define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 55)
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#define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
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#define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
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IRIS_DIRTY_SAMPLER_STATES_CS | \
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IRIS_DIRTY_UNCOMPILED_CS | \
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IRIS_DIRTY_CONSTANTS_CS | \
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IRIS_DIRTY_BINDINGS_CS)
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IRIS_DIRTY_BINDINGS_CS | \
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IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
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#define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
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@@ -133,14 +133,15 @@ iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
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iris_update_compiled_shaders(ice);
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if (ice->state.dirty & IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES) {
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bool draw_aux_buffer_disabled[BRW_MAX_DRAW_BUFFERS] = { };
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for (gl_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++) {
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if (ice->shaders.prog[stage]) {
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if (ice->shaders.prog[stage])
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iris_predraw_resolve_inputs(ice, batch, draw_aux_buffer_disabled,
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stage, true);
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}
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}
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iris_predraw_resolve_framebuffer(ice, batch, draw_aux_buffer_disabled);
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}
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iris_binder_reserve_3d(ice);
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@@ -215,8 +216,10 @@ iris_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *grid)
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/* We can't do resolves on the compute engine, so awkwardly, we have to
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* do them on the render batch...
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*/
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if (ice->state.dirty & IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES) {
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iris_predraw_resolve_inputs(ice, &ice->batches[IRIS_BATCH_RENDER], NULL,
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MESA_SHADER_COMPUTE, false);
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}
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iris_batch_maybe_flush(batch, 1500);
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@@ -971,6 +971,7 @@ iris_bind_blend_state(struct pipe_context *ctx, void *state)
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ice->state.dirty |= IRIS_DIRTY_PS_BLEND;
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ice->state.dirty |= IRIS_DIRTY_BLEND_STATE;
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ice->state.dirty |= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES;
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ice->state.dirty |= ice->state.dirty_for_nos[IRIS_NOS_BLEND];
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}
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@@ -1083,6 +1084,9 @@ iris_bind_zsa_state(struct pipe_context *ctx, void *state)
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if (cso_changed(alpha.func))
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ice->state.dirty |= IRIS_DIRTY_BLEND_STATE;
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if (cso_changed(depth_writes_enabled))
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ice->state.dirty |= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES;
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ice->state.depth_writes_enabled = new_cso->depth_writes_enabled;
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ice->state.stencil_writes_enabled = new_cso->stencil_writes_enabled;
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}
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@@ -1986,6 +1990,9 @@ iris_set_shader_images(struct pipe_context *ctx,
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}
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ice->state.dirty |= IRIS_DIRTY_BINDINGS_VS << stage;
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ice->state.dirty |=
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stage == MESA_SHADER_COMPUTE ? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
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: IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES;
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/* Broadwell also needs brw_image_params re-uploaded */
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if (GEN_GEN < 9) {
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@@ -2021,6 +2028,9 @@ iris_set_sampler_views(struct pipe_context *ctx,
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}
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ice->state.dirty |= (IRIS_DIRTY_BINDINGS_VS << stage);
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ice->state.dirty |=
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stage == MESA_SHADER_COMPUTE ? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
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: IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES;
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}
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/**
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@@ -2359,6 +2369,8 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
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/* Render target change */
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ice->state.dirty |= IRIS_DIRTY_BINDINGS_FS;
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ice->state.dirty |= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES;
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ice->state.dirty |= ice->state.dirty_for_nos[IRIS_NOS_FRAMEBUFFER];
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#if GEN_GEN == 11
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