From 66a275d50f8f7a431e3d9e6c38b64fa73a7e55ba Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Fri, 28 May 2021 15:41:56 +0200 Subject: [PATCH] ir3: Fix shared reg delay Based on computerator experiments, this is actually 6, including for movmsk. Part-of: --- src/freedreno/ir3/ir3_delay.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/freedreno/ir3/ir3_delay.c b/src/freedreno/ir3/ir3_delay.c index b272ff3e225..006da3c6729 100644 --- a/src/freedreno/ir3/ir3_delay.c +++ b/src/freedreno/ir3/ir3_delay.c @@ -83,16 +83,13 @@ ir3_delayslots(struct ir3_instruction *assigner, if (is_sfu(assigner) || is_tex(assigner) || is_mem(assigner)) return 0; - if (assigner->opc == OPC_MOVMSK) - return 4; - /* As far as we know, shader outputs don't need any delay. */ if (consumer->opc == OPC_END || consumer->opc == OPC_CHMASK) return 0; /* assigner must be alu: */ if (is_flow(consumer) || is_sfu(consumer) || is_tex(consumer) || - is_mem(consumer)) { + is_mem(consumer) || (assigner->dsts[0]->flags & IR3_REG_SHARED)) { return 6; } else { /* In mergedregs mode, there is an extra 2-cycle penalty when half of