intel: Add the context to the render_target_supported() vtbl method.

We're going to want to provide different answers per chipset
generation.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

src/mesa/drivers/dri/i915/i830_vtbl.c

@@ -593,7 +593,7 @@ static uint32_t i830_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
 };
 
 static bool
-i830_render_target_supported(gl_format format)
+i830_render_target_supported(struct intel_context *intel, gl_format format)
 {
    if (format == MESA_FORMAT_S8_Z24 ||
        format == MESA_FORMAT_X8_Z24 ||

src/mesa/drivers/dri/i915/i915_vtbl.c

@@ -556,7 +556,7 @@ static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
 };
 
 static bool
-i915_render_target_supported(gl_format format)
+i915_render_target_supported(struct intel_context *intel, gl_format format)
 {
    if (format == MESA_FORMAT_S8_Z24 ||
        format == MESA_FORMAT_X8_Z24 ||

src/mesa/drivers/dri/i965/brw_wm.h

@@ -485,7 +485,7 @@ struct gl_shader *brw_new_shader(struct gl_context *ctx, GLuint name, GLuint typ
 struct gl_shader_program *brw_new_shader_program(struct gl_context *ctx, GLuint name);
 
 bool brw_color_buffer_write_enabled(struct brw_context *brw);
-bool brw_render_target_supported(gl_format format);
+bool brw_render_target_supported(struct intel_context *intel, gl_format format);
 void brw_wm_payload_setup(struct brw_context *brw,
 			  struct brw_wm_compile *c);
 bool do_wm_prog(struct brw_context *brw,

src/mesa/drivers/dri/i965/brw_wm_surface_state.c

@@ -361,7 +361,7 @@ brw_format_for_mesa_format(gl_format mesa_format)
 }
 
 bool
-brw_render_target_supported(gl_format format)
+brw_render_target_supported(struct intel_context *intel, gl_format format)
 {
    /* These are not color render targets like the table holds, but we
     * ask the question for FBO completeness.
@@ -690,8 +690,9 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
 	 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
       break;
    default:
-      assert(brw_render_target_supported(irb->Base.Format));
+      assert(brw_render_target_supported(intel, irb->Base.Format));
       format = brw_format_for_mesa_format(irb->Base.Format);
+      break;
    }
 
    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |

src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

@@ -228,7 +228,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
 	 surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
       break;
    default:
-      assert(brw_render_target_supported(irb->Base.Format));
+      assert(brw_render_target_supported(intel, irb->Base.Format));
       surf->ss0.surface_format = brw_format_for_mesa_format(irb->Base.Format);
    }
 

src/mesa/drivers/dri/intel/intel_context.h

@@ -151,7 +151,8 @@ struct intel_context
       void (*assert_not_dirty) (struct intel_context *intel);
 
       void (*debug_batch)(struct intel_context *intel);
-      bool (*render_target_supported)(gl_format format);
+      bool (*render_target_supported)(struct intel_context *intel,
+				      gl_format format);
 
       /** Can HiZ be enabled on a depthbuffer of the given format? */
       bool (*is_hiz_depth_format)(struct intel_context *intel,

src/mesa/drivers/dri/intel/intel_fbo.c

@@ -1363,7 +1363,7 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
       }
 
       if (!intel_span_supports_format(irb->Base.Format) ||
-	  !intel->vtbl.render_target_supported(irb->Base.Format)) {
+	  !intel->vtbl.render_target_supported(intel, irb->Base.Format)) {
 	 DBG("Unsupported texture/renderbuffer format attached: %s\n",
 	     _mesa_get_format_name(irb->Base.Format));
 	 fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT;