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r300: Clean emit code.

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This fixes some state atom check functions from returing wrong emit size.

There is emit code cleanup so that emit function selection is done in init
time instead of runtime.

Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
This commit is contained in:
Pauli Nieminen
2009-08-20 23:02:37 +03:00
parent d1a0ece907
commit 66513ba884
7 changed files with 182 additions and 164 deletions
Download Patch File Download Diff File Expand all files Collapse all files

231
src/mesa/drivers/dri/r300/r300_cmdbuf.c
View File

@@ -74,66 +74,51 @@ static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
#define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
#define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
int cnt;
int extra = 1;
cnt = vpu_count(atom->cmd);
if (r300->radeon.radeonScreen->kernel_mm) {
extra = 5;
}
return cnt ? (cnt * 4) + extra : 0;
}
void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
drm_r300_cmd_header_t cmd;
uint32_t addr, ndw, i;
if (!r300->radeon.radeonScreen->kernel_mm) {
uint32_t dwords;
dwords = (*atom->check) (ctx, atom);
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(atom->cmd, dwords);
END_BATCH();
return;
}
uint32_t addr, ndw;
cmd.u = atom->cmd[0];
addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
ndw = cmd.vpu.count * 4;
if (ndw) {
ndw = atom->check(ctx, atom);
if (r300->vap_flush_needed) {
BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
BEGIN_BATCH_NO_AUTOSTATE(ndw);
/* flush processing vertices */
OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
r300->vap_flush_needed = GL_FALSE;
} else {
BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
}
ndw -= 5;
OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
for (i = 0; i < ndw; i++) {
OUT_BATCH(atom->cmd[i+1]);
}
OUT_BATCH_TABLE(atom->cmd + 1, ndw);
OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
END_BATCH();
}
}
void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
drm_r300_cmd_header_t cmd;
uint32_t addr, ndw, i, sz;
int type, clamp, stride;
uint32_t addr, ndw, sz;
int type, clamp;
if (!r300->radeon.radeonScreen->kernel_mm) {
uint32_t dwords;
dwords = (*atom->check) (ctx, atom);
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(atom->cmd, dwords);
END_BATCH();
return;
}
ndw = atom->check(ctx, atom);
cmd.u = atom->cmd[0];
sz = cmd.r500fp.count;
@@ -144,20 +129,34 @@ void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
addr |= (type << 16);
addr |= (clamp << 17);
stride = type ? 4 : 6;
ndw = sz * stride;
if (ndw) {
BEGIN_BATCH_NO_AUTOSTATE(3 + ndw);
BEGIN_BATCH_NO_AUTOSTATE(ndw);
OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
OUT_BATCH(addr);
ndw-=3;
OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, ndw-1) | RADEON_ONE_REG_WR);
for (i = 0; i < ndw; i++) {
OUT_BATCH(atom->cmd[i+1]);
}
OUT_BATCH_TABLE(atom->cmd + 1, ndw);
END_BATCH();
}
static int check_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
int dw = 0, i;
if (atom->cmd[0] == CP_PACKET2) {
return dw;
}
for(i = 0; i < numtmus; ++i) {
radeonTexObj *t = r300->hw.textures[i];
if (!t && !r300->radeon.radeonScreen->kernel_mm) {
dw += 0;
} else if (t && t->image_override && !t->bo) {
if (!r300->radeon.radeonScreen->kernel_mm)
dw += 2;
} else
dw += 4;
}
return dw;
}
static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
@@ -247,6 +246,14 @@ void r300_emit_scissor(GLcontext *ctx)
OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
END_BATCH();
}
static int check_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
uint32_t dw = 6 + 3 + 16;
if (r300->radeon.radeonScreen->kernel_mm)
dw += 2;
return dw;
}
static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
{
@@ -338,13 +345,23 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
}
}
static int check_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
uint32_t dw;
dw = 6;
if (r300->radeon.radeonScreen->kernel_mm)
dw += 2;
return dw;
}
static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
struct radeon_renderbuffer *rrb;
uint32_t zbpitch;
uint32_t dw;
uint32_t dw = atom->check(ctx, atom);
rrb = radeon_get_depthbuffer(&r300->radeon);
if (!rrb)
@@ -360,9 +377,6 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
}
}
dw = 6;
if (r300->radeon.radeonScreen->kernel_mm)
dw += 2;
BEGIN_BATCH_NO_AUTOSTATE(dw);
OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
@@ -374,46 +388,6 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
END_BATCH();
}
static void emit_gb_misc(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
BEGIN_BATCH_NO_AUTOSTATE(4);
OUT_BATCH(atom->cmd[0]);
OUT_BATCH(atom->cmd[1]);
OUT_BATCH(atom->cmd[2]);
OUT_BATCH(atom->cmd[3]);
END_BATCH();
}
}
static void emit_threshold_misc(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
BEGIN_BATCH_NO_AUTOSTATE(3);
OUT_BATCH(atom->cmd[0]);
OUT_BATCH(atom->cmd[1]);
OUT_BATCH(atom->cmd[2]);
END_BATCH();
}
}
static void emit_shade_misc(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH(atom->cmd[0]);
OUT_BATCH(atom->cmd[1]);
END_BATCH();
}
}
static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
@@ -431,7 +405,7 @@ static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom
format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
}
BEGIN_BATCH_NO_AUTOSTATE(5);
BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
OUT_BATCH(atom->cmd[0]);
atom->cmd[1] &= ~0xf;
atom->cmd[1] |= format;
@@ -442,6 +416,11 @@ static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom
END_BATCH();
}
static int check_never(GLcontext *ctx, struct radeon_state_atom *atom)
{
return 0;
}
static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
{
return atom->cmd_size;
@@ -458,28 +437,29 @@ static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
return cnt ? cnt + 1 : 0;
}
int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
{
int cnt;
cnt = vpu_count(atom->cmd);
return cnt ? (cnt * 4) + 1 : 0;
}
int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom)
{
int cnt;
r300ContextPtr r300 = R300_CONTEXT(ctx);
int extra = 1;
cnt = r500fp_count(atom->cmd);
return cnt ? (cnt * 6) + 1 : 0;
if (r300->radeon.radeonScreen->kernel_mm)
extra = 3;
return cnt ? (cnt * 6) + extra : 0;
}
int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
{
int cnt;
r300ContextPtr r300 = R300_CONTEXT(ctx);
int extra = 1;
cnt = r500fp_count(atom->cmd);
if (r300->radeon.radeonScreen->kernel_mm)
extra = 3;
cnt = r500fp_count(atom->cmd);
return cnt ? (cnt * 4) + 1 : 0;
return cnt ? (cnt * 4) + extra : 0;
}
#define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
@@ -569,9 +549,12 @@ void r300InitCmdBuf(r300ContextPtr r300)
ALLOC_STATE(gb_enable, always, 2, 0);
r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
} else {
ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
}
r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
r300->hw.gb_misc.emit = emit_gb_misc;
ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
@@ -588,9 +571,12 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
ALLOC_STATE(ga_line_stipple, always, 4, 0);
r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
ALLOC_STATE(shade, always, 2, 0);
} else {
ALLOC_STATE(shade, never, 2, 0);
}
r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
r300->hw.shade.emit = emit_shade_misc;
ALLOC_STATE(shade2, always, 4, 0);
r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
ALLOC_STATE(polygon_mode, always, 4, 0);
@@ -639,10 +625,13 @@ void r300InitCmdBuf(r300ContextPtr r300)
ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.r500fp.emit = emit_r500fp;
ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.r500fp_const.emit = emit_r500fp;
} else {
ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
@@ -686,15 +675,18 @@ void r300InitCmdBuf(r300ContextPtr r300)
}
ALLOC_STATE(rop, always, 2, 0);
r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
r300->hw.cb.emit = &emit_cb_offset;
ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
} else {
ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
}
r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
r300->hw.rb3d_discard_src_pixel_lte_threshold.emit = emit_threshold_misc;
ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
r300->hw.zs.cmd[R300_ZS_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
@@ -704,7 +696,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
r300->hw.zstencil_format.emit = emit_zstencil_format;
ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
r300->hw.zb.emit = emit_zb_offset;
ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
@@ -718,20 +710,37 @@ void r300InitCmdBuf(r300ContextPtr r300)
/* VPU only on TCL */
if (has_tcl) {
int i;
ALLOC_STATE(vap_flush, always, 10, 0);
/* flush processing vertices */
r300->hw.vap_flush.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
r300->hw.vap_flush.cmd[1] = 0;
r300->hw.vap_flush.cmd[2] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DSTCACHE_CTLSTAT, 1);
r300->hw.vap_flush.cmd[3] = R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D;
r300->hw.vap_flush.cmd[4] = cmdpacket0(r300->radeon.radeonScreen, RADEON_WAIT_UNTIL, 1);
r300->hw.vap_flush.cmd[5] = RADEON_WAIT_3D_IDLECLEAN;
r300->hw.vap_flush.cmd[6] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
r300->hw.vap_flush.cmd[7] = 0xffffff;
r300->hw.vap_flush.cmd[8] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
r300->hw.vap_flush.cmd[9] = 0;
ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
r300->hw.vpi.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vpi.emit = emit_vpu;
if (is_r500) {
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
@@ -739,17 +748,20 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.vpucp[i].cmd[0] =
cmdvpu(r300->radeon.radeonScreen,
R500_PVS_UCP_START + i, 1);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vpucp[i].emit = emit_vpu;
}
} else {
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
@@ -757,6 +769,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.vpucp[i].cmd[0] =
cmdvpu(r300->radeon.radeonScreen,
R300_PVS_UCP_START + i, 1);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vpucp[i].emit = emit_vpu;
}
}
@@ -781,7 +794,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
ALLOC_STATE(tex.offset, variable, 1, 0);
ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
r300->hw.tex.offset.emit = &emit_tex_offsets;

3
src/mesa/drivers/dri/r300/r300_context.c
View File

@@ -212,11 +212,8 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes
static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
{
r300ContextPtr r300 = (r300ContextPtr)radeon;
BATCH_LOCALS(radeon);
r300->vap_flush_needed = GL_TRUE;
cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);

2
src/mesa/drivers/dri/r300/r300_context.h
View File

@@ -350,6 +350,7 @@ struct r300_hw_state {
struct radeon_state_atom zb_hiz_offset; /* (4F44) */
struct radeon_state_atom zb_hiz_pitch; /* (4F54) */
struct radeon_state_atom vap_flush;
struct radeon_state_atom vpi; /* vp instructions */
struct radeon_state_atom vpp; /* vp parameters */
struct radeon_state_atom vps; /* vertex point size (?) */
@@ -524,7 +525,6 @@ struct r300_context {
struct r300_swtcl_info swtcl;
struct r300_vertex_buffer vbuf;
struct r300_index_buffer ind_buf;
GLboolean vap_flush_needed;
uint32_t fallback;

9
src/mesa/drivers/dri/r300/r300_ioctl.c
View File

@@ -551,6 +551,7 @@ static void r300EmitClearState(GLcontext * ctx)
struct radeon_state_atom vpu;
uint32_t _cmd[10];
R300_STATECHANGE(r300, pvs);
R300_STATECHANGE(r300, vap_flush);
R300_STATECHANGE(r300, vpi);
BEGIN_BATCH(4);
@@ -592,7 +593,13 @@ static void r300EmitClearState(GLcontext * ctx)
PVS_SRC_REG_INPUT, NEGATE_NONE);
vpu.cmd[8] = 0x0;
r300->vap_flush_needed = GL_TRUE;
{
int dwords = r300->hw.vap_flush.check(ctx,&r300->hw.vap_flush);
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(r300->hw.vap_flush.cmd, dwords);
END_BATCH();
}
emit_vpu(ctx, &vpu);
}
}

1
src/mesa/drivers/dri/r300/r300_state.c
View File

@@ -371,6 +371,7 @@ static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
ip = (GLint *)ctx->Transform._ClipUserPlane[p];
R300_STATECHANGE( rmesa, vap_flush );
R300_STATECHANGE( rmesa, vpucp[p] );
rmesa->hw.vpucp[p].cmd[R300_VPUCP_X] = ip[0];
rmesa->hw.vpucp[p].cmd[R300_VPUCP_Y] = ip[1];

3
src/mesa/drivers/dri/r300/r300_vertprog.c
View File

@@ -298,6 +298,8 @@ static void r300EmitVertexProgram(r300ContextPtr r300, int dest, struct r300_ver
assert((code->length > 0) && (code->length % 4 == 0));
R300_STATECHANGE( r300, vap_flush );
switch ((dest >> 8) & 0xf) {
case 0:
R300_STATECHANGE(r300, vpi);
@@ -335,6 +337,7 @@ void r300SetupVertexProgram(r300ContextPtr rmesa)
((drm_r300_cmd_header_t *) rmesa->hw.vpi.cmd)->vpu.count = 0;
((drm_r300_cmd_header_t *) rmesa->hw.vps.cmd)->vpu.count = 0;
R300_STATECHANGE(rmesa, vap_flush);
R300_STATECHANGE(rmesa, vpp);
param_count = r300VertexProgUpdateParams(ctx, prog, (float *)&rmesa->hw.vpp.cmd[R300_VPP_PARAM_0]);
bump_vpu_count(rmesa->hw.vpp.cmd, param_count);

5
src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
View File

@@ -71,10 +71,7 @@ void rcommonBeginBatch(radeonContextPtr rmesa,
*/
#define OUT_BATCH_TABLE(ptr,n) \
do { \
int _i; \
for (_i=0; _i < n; _i++) {\
radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, ptr[_i]);\
}\
radeon_cs_write_table(b_l_rmesa->cmdbuf.cs, (ptr), (n));\
} while(0)
/**