radv: update configuring viewport/scissor on GFX12
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29417>
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@@ -2898,32 +2898,55 @@ radv_get_viewport_zmin_zmax(struct radv_cmd_buffer *cmd_buffer, const VkViewport
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static void
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radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
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{
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const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
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assert(d->vk.vp.viewport_count);
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radeon_set_context_reg_seq(cmd_buffer->cs, R_02843C_PA_CL_VPORT_XSCALE, d->vk.vp.viewport_count * 6);
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for (unsigned i = 0; i < d->vk.vp.viewport_count; i++) {
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float zscale, ztranslate;
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if (pdev->info.gfx_level >= GFX12) {
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radeon_set_context_reg_seq(cmd_buffer->cs, R_02843C_PA_CL_VPORT_XSCALE, d->vk.vp.viewport_count * 8);
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radv_get_viewport_zscale_ztranslate(cmd_buffer, i, &zscale, &ztranslate);
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for (unsigned i = 0; i < d->vk.vp.viewport_count; i++) {
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float zscale, ztranslate, zmin, zmax;
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].scale[0]));
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].translate[0]));
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].scale[1]));
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].translate[1]));
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radeon_emit(cmd_buffer->cs, fui(zscale));
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radeon_emit(cmd_buffer->cs, fui(ztranslate));
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}
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radv_get_viewport_zscale_ztranslate(cmd_buffer, i, &zscale, &ztranslate);
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radv_get_viewport_zmin_zmax(cmd_buffer, &d->vk.vp.viewports[i], &zmin, &zmax);
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radeon_set_context_reg_seq(cmd_buffer->cs, R_0282D0_PA_SC_VPORT_ZMIN_0, d->vk.vp.viewport_count * 2);
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for (unsigned i = 0; i < d->vk.vp.viewport_count; i++) {
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float zmin, zmax;
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].scale[0]));
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].translate[0]));
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].scale[1]));
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].translate[1]));
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radeon_emit(cmd_buffer->cs, fui(zscale));
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radeon_emit(cmd_buffer->cs, fui(ztranslate));
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radeon_emit(cmd_buffer->cs, fui(zmin));
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radeon_emit(cmd_buffer->cs, fui(zmax));
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}
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} else {
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radeon_set_context_reg_seq(cmd_buffer->cs, R_02843C_PA_CL_VPORT_XSCALE, d->vk.vp.viewport_count * 6);
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radv_get_viewport_zmin_zmax(cmd_buffer, &d->vk.vp.viewports[i], &zmin, &zmax);
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for (unsigned i = 0; i < d->vk.vp.viewport_count; i++) {
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float zscale, ztranslate;
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radeon_emit(cmd_buffer->cs, fui(zmin));
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radeon_emit(cmd_buffer->cs, fui(zmax));
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radv_get_viewport_zscale_ztranslate(cmd_buffer, i, &zscale, &ztranslate);
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].scale[0]));
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].translate[0]));
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].scale[1]));
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radeon_emit(cmd_buffer->cs, fui(d->hw_vp.xform[i].translate[1]));
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radeon_emit(cmd_buffer->cs, fui(zscale));
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radeon_emit(cmd_buffer->cs, fui(ztranslate));
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}
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radeon_set_context_reg_seq(cmd_buffer->cs, R_0282D0_PA_SC_VPORT_ZMIN_0, d->vk.vp.viewport_count * 2);
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for (unsigned i = 0; i < d->vk.vp.viewport_count; i++) {
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float zmin, zmax;
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radv_get_viewport_zmin_zmax(cmd_buffer, &d->vk.vp.viewports[i], &zmin, &zmax);
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radeon_emit(cmd_buffer->cs, fui(zmin));
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radeon_emit(cmd_buffer->cs, fui(zmax));
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}
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}
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}
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@@ -2957,6 +2980,8 @@ radv_intersect_scissor(const VkRect2D *a, const VkRect2D *b)
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static void
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radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
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{
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const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
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struct radeon_cmdbuf *cs = cmd_buffer->cs;
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@@ -2968,10 +2993,23 @@ radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
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VkRect2D viewport_scissor = radv_scissor_from_viewport(d->vk.vp.viewports + i);
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VkRect2D scissor = radv_intersect_scissor(&d->vk.vp.scissors[i], &viewport_scissor);
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radeon_emit(cs, S_028250_TL_X(scissor.offset.x) | S_028250_TL_Y_GFX6(scissor.offset.y) |
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S_028250_WINDOW_OFFSET_DISABLE(1));
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radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
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S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
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uint32_t minx = scissor.offset.x;
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uint32_t miny = scissor.offset.y;
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uint32_t maxx = minx + scissor.extent.width;
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uint32_t maxy = miny + scissor.extent.height;
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if (pdev->info.gfx_level >= GFX12) {
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/* On GFX12, an empty scissor must be done like this because the bottom-right bounds are inclusive. */
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if (maxx == 0 || maxy == 0) {
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minx = miny = maxx = maxy = 1;
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}
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radeon_emit(cs, S_028250_TL_X(minx) | S_028250_TL_Y_GFX12(miny));
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radeon_emit(cs, S_028254_BR_X(maxx - 1) | S_028254_BR_Y(maxy - 1));
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} else {
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radeon_emit(cs, S_028250_TL_X(minx) | S_028250_TL_Y_GFX6(miny) | S_028250_WINDOW_OFFSET_DISABLE(1));
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radeon_emit(cs, S_028254_BR_X(maxx) | S_028254_BR_Y(maxy));
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}
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}
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}
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