radv: fix shaders cache corruption with indirect pipeline binds
Indirect pipeline binds force indirect descriptor sets and this needs
to be in the shader stage key, otherwise two shaders might result in
the same pipeline cache key.
Fixes: b1ba02e707
("radv: force using indirect descriptor sets for indirect compute pipelines")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30209>
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commit
65acc81e9d
@@ -1121,7 +1121,7 @@ void
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radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir,
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const struct radv_shader_layout *layout, const struct radv_shader_stage_key *stage_key,
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const struct radv_graphics_state_key *gfx_state, const enum radv_pipeline_type pipeline_type,
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bool consider_force_vrs, bool is_indirect_bindable, struct radv_shader_info *info)
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bool consider_force_vrs, struct radv_shader_info *info)
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{
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const struct radv_physical_device *pdev = radv_device_physical(device);
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struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
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@@ -1232,7 +1232,7 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
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info->user_data_0 = radv_get_user_data_0(device, info);
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info->merged_shader_compiled_separately = radv_is_merged_shader_compiled_separately(device, info);
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info->force_indirect_desc_sets = info->merged_shader_compiled_separately || is_indirect_bindable;
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info->force_indirect_desc_sets = info->merged_shader_compiled_separately || stage_key->indirect_bindable;
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switch (nir->info.stage) {
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case MESA_SHADER_COMPUTE:
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