turnip: add tu_pipeline.h
Also drop unused tu_pipeline_key. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17811>
This commit is contained in:
Chia-I Wu
@@ -25,6 +25,8 @@
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "tu_pipeline.h"
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#include "common/freedreno_guardband.h"
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#include "tu_private.h"
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264
src/freedreno/vulkan/tu_pipeline.h
Normal file
264
src/freedreno/vulkan/tu_pipeline.h
Normal file
@@ -0,0 +1,264 @@
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/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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* SPDX-License-Identifier: MIT
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*/
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#ifndef TU_PIPELINE_H
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#define TU_PIPELINE_H
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#include "tu_common.h"
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#include "tu_cs.h"
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#include "tu_descriptor_set.h"
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#include "tu_shader.h"
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#include "tu_suballoc.h"
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enum tu_dynamic_state
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{
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/* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
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TU_DYNAMIC_STATE_SAMPLE_LOCATIONS = VK_DYNAMIC_STATE_STENCIL_REFERENCE + 1,
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TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
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TU_DYNAMIC_STATE_RB_STENCIL_CNTL,
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TU_DYNAMIC_STATE_VB_STRIDE,
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TU_DYNAMIC_STATE_RASTERIZER_DISCARD,
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TU_DYNAMIC_STATE_BLEND,
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TU_DYNAMIC_STATE_COUNT,
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/* no associated draw state: */
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TU_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY = TU_DYNAMIC_STATE_COUNT,
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TU_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE,
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TU_DYNAMIC_STATE_LOGIC_OP,
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TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE,
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/* re-use the line width enum as it uses GRAS_SU_CNTL: */
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TU_DYNAMIC_STATE_GRAS_SU_CNTL = VK_DYNAMIC_STATE_LINE_WIDTH,
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};
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struct cache_entry;
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struct tu_pipeline_cache
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{
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struct vk_object_base base;
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struct tu_device *device;
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pthread_mutex_t mutex;
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uint32_t total_size;
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uint32_t table_size;
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uint32_t kernel_count;
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struct cache_entry **hash_table;
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bool modified;
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VkAllocationCallbacks alloc;
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};
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VK_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, base, VkPipelineCache,
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VK_OBJECT_TYPE_PIPELINE_CACHE)
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struct tu_lrz_pipeline
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{
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uint32_t force_disable_mask;
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bool fs_has_kill;
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bool force_late_z;
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bool early_fragment_tests;
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};
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struct tu_compiled_shaders
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{
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struct vk_pipeline_cache_object base;
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struct tu_push_constant_range push_consts[MESA_SHADER_STAGES];
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uint8_t active_desc_sets;
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bool multi_pos_output;
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struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
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};
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extern const struct vk_pipeline_cache_object_ops tu_shaders_ops;
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static bool inline
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tu6_shared_constants_enable(const struct tu_pipeline_layout *layout,
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const struct ir3_compiler *compiler)
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{
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return layout->push_constant_size > 0 &&
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layout->push_constant_size <= (compiler->shared_consts_size * 16);
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}
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struct tu_program_descriptor_linkage
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{
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struct ir3_const_state const_state;
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uint32_t constlen;
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struct tu_push_constant_range push_consts;
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};
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struct tu_pipeline_executable {
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gl_shader_stage stage;
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struct ir3_info stats;
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bool is_binning;
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char *nir_from_spirv;
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char *nir_final;
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char *disasm;
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};
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struct tu_pipeline
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{
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struct vk_object_base base;
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struct tu_cs cs;
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struct tu_suballoc_bo bo;
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/* Separate BO for private memory since it should GPU writable */
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struct tu_bo *pvtmem_bo;
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bool need_indirect_descriptor_sets;
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VkShaderStageFlags active_stages;
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uint32_t active_desc_sets;
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/* mask of enabled dynamic states
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* if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
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*/
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uint32_t dynamic_state_mask;
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struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
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/* for dynamic states which use the same register: */
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uint32_t gras_su_cntl, gras_su_cntl_mask;
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uint32_t rb_depth_cntl, rb_depth_cntl_mask;
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uint32_t rb_stencil_cntl, rb_stencil_cntl_mask;
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uint32_t pc_raster_cntl, pc_raster_cntl_mask;
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uint32_t vpc_unknown_9107, vpc_unknown_9107_mask;
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uint32_t stencil_wrmask;
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unsigned num_rts;
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uint32_t rb_mrt_control[MAX_RTS], rb_mrt_control_mask;
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uint32_t rb_mrt_blend_control[MAX_RTS];
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uint32_t sp_blend_cntl, sp_blend_cntl_mask;
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uint32_t rb_blend_cntl, rb_blend_cntl_mask;
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uint32_t color_write_enable, blend_enable;
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bool logic_op_enabled, rop_reads_dst;
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bool rasterizer_discard;
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bool rb_depth_cntl_disable;
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enum a5xx_line_mode line_mode;
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/* draw states for the pipeline */
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struct tu_draw_state load_state, rast_state;
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struct tu_draw_state prim_order_state_sysmem, prim_order_state_gmem;
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/* for vertex buffers state */
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uint32_t num_vbs;
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struct tu_push_constant_range shared_consts;
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struct
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{
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struct tu_draw_state config_state;
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struct tu_draw_state state;
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struct tu_draw_state binning_state;
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struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
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} program;
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struct
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{
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struct tu_draw_state state;
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struct tu_draw_state binning_state;
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} vi;
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struct
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{
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enum pc_di_primtype primtype;
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bool primitive_restart;
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} ia;
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struct
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{
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uint32_t patch_type;
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uint32_t param_stride;
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bool upper_left_domain_origin;
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} tess;
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struct
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{
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uint32_t local_size[3];
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uint32_t subgroup_size;
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} compute;
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bool provoking_vertex_last;
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struct tu_lrz_pipeline lrz;
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/* In other words - framebuffer fetch support */
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bool raster_order_attachment_access;
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bool subpass_feedback_loop_ds;
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bool z_negative_one_to_one;
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/* memory bandwidth cost (in bytes) for color attachments */
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uint32_t color_bandwidth_per_sample;
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uint32_t depth_cpp_per_sample;
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uint32_t stencil_cpp_per_sample;
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void *executables_mem_ctx;
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/* tu_pipeline_executable */
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struct util_dynarray executables;
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};
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VK_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, base, VkPipeline,
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VK_OBJECT_TYPE_PIPELINE)
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void
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tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport, uint32_t num_viewport,
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bool z_negative_one_to_one);
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void
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tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scs, uint32_t scissor_count);
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void
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tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc);
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void
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tu6_emit_depth_bias(struct tu_cs *cs,
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float constant_factor,
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float clamp,
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float slope_factor);
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uint32_t tu6_rb_mrt_control_rop(VkLogicOp op, bool *rop_reads_dst);
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struct tu_pvtmem_config {
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uint64_t iova;
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uint32_t per_fiber_size;
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uint32_t per_sp_size;
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bool per_wave;
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};
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void
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tu6_emit_xs_config(struct tu_cs *cs,
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gl_shader_stage stage,
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const struct ir3_shader_variant *xs);
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void
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tu6_emit_xs(struct tu_cs *cs,
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gl_shader_stage stage,
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const struct ir3_shader_variant *xs,
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const struct tu_pvtmem_config *pvtmem,
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uint64_t binary_iova);
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void
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tu6_emit_vpc(struct tu_cs *cs,
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const struct ir3_shader_variant *vs,
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const struct ir3_shader_variant *hs,
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const struct ir3_shader_variant *ds,
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const struct ir3_shader_variant *gs,
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const struct ir3_shader_variant *fs,
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uint32_t patch_control_points);
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void
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tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);
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#endif /* TU_PIPELINE_H */
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@@ -36,6 +36,7 @@
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#include "tu_formats.h"
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#include "tu_image.h"
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#include "tu_perfetto.h"
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#include "tu_pipeline.h"
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#include "tu_query.h"
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#include "tu_shader.h"
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#include "tu_suballoc.h"
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@@ -202,29 +203,6 @@ bool
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tu_physical_device_extension_supported(struct tu_physical_device *dev,
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const char *name);
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struct cache_entry;
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struct tu_pipeline_cache
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{
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struct vk_object_base base;
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struct tu_device *device;
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pthread_mutex_t mutex;
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uint32_t total_size;
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uint32_t table_size;
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uint32_t kernel_count;
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struct cache_entry **hash_table;
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bool modified;
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VkAllocationCallbacks alloc;
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};
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struct tu_pipeline_key
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{
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};
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/* queue types */
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#define TU_QUEUE_GENERAL 0
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@@ -484,25 +462,6 @@ tu_device_lookup_bo(struct tu_device *device, uint32_t handle)
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VkResult
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tu_get_scratch_bo(struct tu_device *dev, uint64_t size, struct tu_bo **bo);
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enum tu_dynamic_state
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{
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/* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
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TU_DYNAMIC_STATE_SAMPLE_LOCATIONS = VK_DYNAMIC_STATE_STENCIL_REFERENCE + 1,
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TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
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TU_DYNAMIC_STATE_RB_STENCIL_CNTL,
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TU_DYNAMIC_STATE_VB_STRIDE,
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TU_DYNAMIC_STATE_RASTERIZER_DISCARD,
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TU_DYNAMIC_STATE_BLEND,
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TU_DYNAMIC_STATE_COUNT,
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/* no associated draw state: */
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TU_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY = TU_DYNAMIC_STATE_COUNT,
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TU_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE,
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TU_DYNAMIC_STATE_LOGIC_OP,
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TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE,
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/* re-use the line width enum as it uses GRAS_SU_CNTL: */
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TU_DYNAMIC_STATE_GRAS_SU_CNTL = VK_DYNAMIC_STATE_LINE_WIDTH,
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};
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enum tu_draw_state_group_id
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{
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TU_DRAW_STATE_PROGRAM_CONFIG,
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@@ -914,14 +873,6 @@ enum tu_lrz_direction {
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TU_LRZ_GREATER,
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};
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struct tu_lrz_pipeline
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{
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uint32_t force_disable_mask;
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bool fs_has_kill;
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bool force_late_z;
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bool early_fragment_tests;
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};
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struct tu_lrz_state
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{
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/* Depth/Stencil image currently on use to do LRZ */
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@@ -1354,153 +1305,6 @@ struct tu_event
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struct tu_bo *bo;
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};
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struct tu_compiled_shaders
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{
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struct vk_pipeline_cache_object base;
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struct tu_push_constant_range push_consts[MESA_SHADER_STAGES];
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uint8_t active_desc_sets;
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bool multi_pos_output;
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struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
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};
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extern const struct vk_pipeline_cache_object_ops tu_shaders_ops;
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static bool inline
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tu6_shared_constants_enable(const struct tu_pipeline_layout *layout,
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const struct ir3_compiler *compiler)
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{
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return layout->push_constant_size > 0 &&
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layout->push_constant_size <= (compiler->shared_consts_size * 16);
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}
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struct tu_program_descriptor_linkage
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{
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struct ir3_const_state const_state;
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uint32_t constlen;
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struct tu_push_constant_range push_consts;
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};
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struct tu_pipeline_executable {
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gl_shader_stage stage;
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struct ir3_info stats;
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bool is_binning;
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char *nir_from_spirv;
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char *nir_final;
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char *disasm;
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};
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struct tu_pipeline
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{
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struct vk_object_base base;
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struct tu_cs cs;
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struct tu_suballoc_bo bo;
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/* Separate BO for private memory since it should GPU writable */
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struct tu_bo *pvtmem_bo;
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bool need_indirect_descriptor_sets;
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VkShaderStageFlags active_stages;
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uint32_t active_desc_sets;
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/* mask of enabled dynamic states
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* if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
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*/
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uint32_t dynamic_state_mask;
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struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
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/* for dynamic states which use the same register: */
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uint32_t gras_su_cntl, gras_su_cntl_mask;
|
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uint32_t rb_depth_cntl, rb_depth_cntl_mask;
|
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uint32_t rb_stencil_cntl, rb_stencil_cntl_mask;
|
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uint32_t pc_raster_cntl, pc_raster_cntl_mask;
|
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uint32_t vpc_unknown_9107, vpc_unknown_9107_mask;
|
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uint32_t stencil_wrmask;
|
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unsigned num_rts;
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uint32_t rb_mrt_control[MAX_RTS], rb_mrt_control_mask;
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uint32_t rb_mrt_blend_control[MAX_RTS];
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uint32_t sp_blend_cntl, sp_blend_cntl_mask;
|
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uint32_t rb_blend_cntl, rb_blend_cntl_mask;
|
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uint32_t color_write_enable, blend_enable;
|
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bool logic_op_enabled, rop_reads_dst;
|
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bool rasterizer_discard;
|
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|
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bool rb_depth_cntl_disable;
|
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|
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enum a5xx_line_mode line_mode;
|
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/* draw states for the pipeline */
|
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struct tu_draw_state load_state, rast_state;
|
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struct tu_draw_state prim_order_state_sysmem, prim_order_state_gmem;
|
||||
|
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/* for vertex buffers state */
|
||||
uint32_t num_vbs;
|
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|
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struct tu_push_constant_range shared_consts;
|
||||
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struct
|
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{
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struct tu_draw_state config_state;
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struct tu_draw_state state;
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struct tu_draw_state binning_state;
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struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
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} program;
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struct
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{
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struct tu_draw_state state;
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struct tu_draw_state binning_state;
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} vi;
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struct
|
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{
|
||||
enum pc_di_primtype primtype;
|
||||
bool primitive_restart;
|
||||
} ia;
|
||||
|
||||
struct
|
||||
{
|
||||
uint32_t patch_type;
|
||||
uint32_t param_stride;
|
||||
bool upper_left_domain_origin;
|
||||
} tess;
|
||||
|
||||
struct
|
||||
{
|
||||
uint32_t local_size[3];
|
||||
uint32_t subgroup_size;
|
||||
} compute;
|
||||
|
||||
bool provoking_vertex_last;
|
||||
|
||||
struct tu_lrz_pipeline lrz;
|
||||
|
||||
/* In other words - framebuffer fetch support */
|
||||
bool raster_order_attachment_access;
|
||||
bool subpass_feedback_loop_ds;
|
||||
|
||||
bool z_negative_one_to_one;
|
||||
|
||||
/* memory bandwidth cost (in bytes) for color attachments */
|
||||
uint32_t color_bandwidth_per_sample;
|
||||
|
||||
uint32_t depth_cpp_per_sample;
|
||||
uint32_t stencil_cpp_per_sample;
|
||||
|
||||
void *executables_mem_ctx;
|
||||
/* tu_pipeline_executable */
|
||||
struct util_dynarray executables;
|
||||
};
|
||||
|
||||
void
|
||||
tu6_clear_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs, struct tu_image* image, const VkClearValue *value);
|
||||
|
||||
@@ -1547,22 +1351,6 @@ tu_lrz_sysmem_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs);
|
||||
void
|
||||
tu_lrz_disable_during_renderpass(struct tu_cmd_buffer *cmd);
|
||||
|
||||
void
|
||||
tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport, uint32_t num_viewport,
|
||||
bool z_negative_one_to_one);
|
||||
|
||||
void
|
||||
tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scs, uint32_t scissor_count);
|
||||
|
||||
void
|
||||
tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc);
|
||||
|
||||
void
|
||||
tu6_emit_depth_bias(struct tu_cs *cs,
|
||||
float constant_factor,
|
||||
float clamp,
|
||||
float slope_factor);
|
||||
|
||||
void tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits samples,
|
||||
enum a5xx_line_mode line_mode);
|
||||
|
||||
@@ -1570,44 +1358,11 @@ void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_
|
||||
|
||||
void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
|
||||
|
||||
uint32_t tu6_rb_mrt_control_rop(VkLogicOp op, bool *rop_reads_dst);
|
||||
|
||||
void tu_disable_draw_states(struct tu_cmd_buffer *cmd, struct tu_cs *cs);
|
||||
|
||||
void tu6_apply_depth_bounds_workaround(struct tu_device *device,
|
||||
uint32_t *rb_depth_cntl);
|
||||
|
||||
struct tu_pvtmem_config {
|
||||
uint64_t iova;
|
||||
uint32_t per_fiber_size;
|
||||
uint32_t per_sp_size;
|
||||
bool per_wave;
|
||||
};
|
||||
|
||||
void
|
||||
tu6_emit_xs_config(struct tu_cs *cs,
|
||||
gl_shader_stage stage,
|
||||
const struct ir3_shader_variant *xs);
|
||||
|
||||
void
|
||||
tu6_emit_xs(struct tu_cs *cs,
|
||||
gl_shader_stage stage,
|
||||
const struct ir3_shader_variant *xs,
|
||||
const struct tu_pvtmem_config *pvtmem,
|
||||
uint64_t binary_iova);
|
||||
|
||||
void
|
||||
tu6_emit_vpc(struct tu_cs *cs,
|
||||
const struct ir3_shader_variant *vs,
|
||||
const struct ir3_shader_variant *hs,
|
||||
const struct ir3_shader_variant *ds,
|
||||
const struct ir3_shader_variant *gs,
|
||||
const struct ir3_shader_variant *fs,
|
||||
uint32_t patch_control_points);
|
||||
|
||||
void
|
||||
tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);
|
||||
|
||||
void
|
||||
tu_resolve_sysmem(struct tu_cmd_buffer *cmd,
|
||||
struct tu_cs *cs,
|
||||
@@ -1740,10 +1495,6 @@ VK_DEFINE_NONDISP_HANDLE_CASTS(tu_device_memory, base, VkDeviceMemory,
|
||||
VK_DEFINE_NONDISP_HANDLE_CASTS(tu_event, base, VkEvent, VK_OBJECT_TYPE_EVENT)
|
||||
VK_DEFINE_NONDISP_HANDLE_CASTS(tu_framebuffer, base, VkFramebuffer,
|
||||
VK_OBJECT_TYPE_FRAMEBUFFER)
|
||||
VK_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline_cache, base, VkPipelineCache,
|
||||
VK_OBJECT_TYPE_PIPELINE_CACHE)
|
||||
VK_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, base, VkPipeline,
|
||||
VK_OBJECT_TYPE_PIPELINE)
|
||||
VK_DEFINE_NONDISP_HANDLE_CASTS(tu_render_pass, base, VkRenderPass,
|
||||
VK_OBJECT_TYPE_RENDER_PASS)
|
||||
VK_DEFINE_NONDISP_HANDLE_CASTS(tu_sampler, base, VkSampler,
|
||||
|
||||
Reference in New Issue
Block a user