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intel/eu/xe2+: Update validation of GRF region size to account for Xe2 reg size

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Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Francisco Jerez
2022-07-15 19:11:04 -07:00
committed by Jordan Justen
parent 00b614a5a7
commit 6423cb9bfa
1 changed files with 2 additions and 2 deletions
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4
src/intel/compiler/brw_eu_validate.c
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@@ -1465,7 +1465,7 @@ region_alignment_rules(const struct brw_isa_info *isa,
unsigned hstride_elements = (num_hstride - 1) * hstride;
unsigned offset = (vstride_elements + hstride_elements) * element_size +
subreg;
ERROR_IF(offset >= 64,
ERROR_IF(offset >= 64 * reg_unit(devinfo),
"A source cannot span more than 2 adjacent GRF registers");
}
@@ -1477,7 +1477,7 @@ region_alignment_rules(const struct brw_isa_info *isa,
unsigned element_size = brw_reg_type_to_size(dst_type);
unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
unsigned offset = ((exec_size - 1) * stride * element_size) + subreg;
ERROR_IF(offset >= 64,
ERROR_IF(offset >= 64 * reg_unit(devinfo),
"A destination cannot span more than 2 adjacent GRF registers");
if (error_msg.str)