pan/mdg: Use PAN_IS_REG

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4792>
This commit is contained in:
Alyssa Rosenzweig
2020-04-27 16:34:53 -04:00
committed by Marge Bot
parent d4600c4340
commit 63eec105b2
6 changed files with 17 additions and 21 deletions

View File

@@ -425,10 +425,6 @@ mir_is_alu_bundle(midgard_bundle *bundle)
return IS_ALU(bundle->tag);
}
/* Registers/SSA are distinguish in the backend by the bottom-most bit */
#define IS_REG (1)
static inline unsigned
make_compiler_temp(compiler_context *ctx)
{
@@ -438,7 +434,7 @@ make_compiler_temp(compiler_context *ctx)
static inline unsigned
make_compiler_temp_reg(compiler_context *ctx)
{
return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
}
static inline unsigned
@@ -454,7 +450,7 @@ nir_src_index(compiler_context *ctx, nir_src *src)
return nir_ssa_index(src->ssa);
else {
assert(!src->reg.indirect);
return (src->reg.reg->index << 1) | IS_REG;
return (src->reg.reg->index << 1) | PAN_IS_REG;
}
}
@@ -465,7 +461,7 @@ nir_dest_index(nir_dest *dst)
return (dst->ssa.index << 1) | 0;
else {
assert(!dst->reg.indirect);
return (dst->reg.reg->index << 1) | IS_REG;
return (dst->reg.reg->index << 1) | PAN_IS_REG;
}
}

View File

@@ -2287,7 +2287,7 @@ midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
/* TODO: Registers? */
unsigned src = ins->src[1];
if (src & IS_REG) continue;
if (src & PAN_IS_REG) continue;
/* There might be a source modifier, too */
if (mir_nontrivial_source2_mod(ins)) continue;

View File

@@ -39,8 +39,8 @@ midgard_opt_copy_prop_reg(compiler_context *ctx, midgard_block *block)
unsigned from = ins->src[1];
unsigned to = ins->dest;
if (!(to & IS_REG)) continue;
if (from & IS_REG) continue;
if (!(to & PAN_IS_REG)) continue;
if (from & PAN_IS_REG) continue;
if (ins->has_inline_constant) continue;
if (ins->has_constants) continue;
@@ -76,8 +76,8 @@ midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
if (to >= SSA_FIXED_MINIMUM) continue;
if (from >= SSA_FIXED_MINIMUM) continue;
if (to & IS_REG) continue;
if (from & IS_REG) continue;
if (to & PAN_IS_REG) continue;
if (from & PAN_IS_REG) continue;
/* Constant propagation is not handled here, either */
if (ins->has_inline_constant) continue;

View File

@@ -71,7 +71,7 @@ midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block)
if (ins->alu.op != midgard_alu_op_imov) continue;
if (!ins->invert) continue;
if (mir_nontrivial_source2_mod_simple(ins)) continue;
if (ins->src[1] & IS_REG) continue;
if (ins->src[1] & PAN_IS_REG) continue;
/* Is it beneficial to propagate? */
if (!mir_single_use(ctx, ins->src[1])) continue;
@@ -230,7 +230,7 @@ mir_strip_inverted(compiler_context *ctx, unsigned node)
static bool
is_ssa_or_constant(unsigned node)
{
return !(node & IS_REG) || (node == SSA_FIXED_REGISTER(26));
return !(node & PAN_IS_REG) || (node == SSA_FIXED_REGISTER(26));
}
bool
@@ -372,7 +372,7 @@ midgard_opt_drop_cmp_invert(compiler_context *ctx, midgard_block *block)
if (ins->type != TAG_ALU_4) continue;
if (!OP_IS_INTEGER_CMP(ins->alu.op)) continue;
if ((ins->src[0] & IS_REG) || (ins->src[1] & IS_REG)) continue;
if ((ins->src[0] & PAN_IS_REG) || (ins->src[1] & PAN_IS_REG)) continue;
if (!mir_single_use(ctx, ins->src[0]) || !mir_single_use(ctx, ins->src[1])) continue;
bool a_inverted = mir_is_inverted(ctx, ins->src[0]);
@@ -406,7 +406,7 @@ midgard_opt_invert_branch(compiler_context *ctx, midgard_block *block)
if (ins->type != TAG_ALU_4) continue;
if (!midgard_is_branch_unit(ins->unit)) continue;
if (!ins->branch.conditional) continue;
if (ins->src[0] & IS_REG) continue;
if (ins->src[0] & PAN_IS_REG) continue;
if (mir_strip_inverted(ctx, ins->src[0])) {
ins->branch.invert_conditional = !ins->branch.invert_conditional;

View File

@@ -68,8 +68,8 @@ midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block)
unsigned frcp = ins->src[1];
unsigned to = ins->dest;
if (frcp & IS_REG) continue;
if (to & IS_REG) continue;
if (frcp & PAN_IS_REG) continue;
if (to & PAN_IS_REG) continue;
bool frcp_found = false;
unsigned frcp_component = 0;
@@ -148,8 +148,8 @@ midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block)
unsigned vary = ins->src[0];
unsigned to = ins->dest;
if (vary & IS_REG) continue;
if (to & IS_REG) continue;
if (vary & PAN_IS_REG) continue;
if (to & PAN_IS_REG) continue;
if (!mir_single_use(ctx, vary)) continue;
/* Check for a varying source. If we find it, we rewrite */

View File

@@ -152,7 +152,7 @@ midgard_promote_uniforms(compiler_context *ctx)
/* We do need the move for safety for a non-SSA dest, or if
* we're being fed into a special class */
bool needs_move = ins->dest & IS_REG;
bool needs_move = ins->dest & PAN_IS_REG;
needs_move |= mir_special_index(ctx, ins->dest);
if (needs_move) {