nak: Rename OpFSOut to OpRegOut

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30402>
This commit is contained in:
Faith Ekstrand
2024-07-27 14:36:20 -05:00
committed by Marge Bot
parent 0b4bfefd6f
commit 63db105014
5 changed files with 14 additions and 14 deletions

View File

@@ -119,7 +119,7 @@ impl SSAUseMap {
pub fn add_block(&mut self, b: &BasicBlock) { pub fn add_block(&mut self, b: &BasicBlock) {
for (ip, instr) in b.instrs.iter().enumerate() { for (ip, instr) in b.instrs.iter().enumerate() {
match &instr.op { match &instr.op {
Op::FSOut(op) => { Op::RegOut(op) => {
for (i, src) in op.srcs.iter().enumerate() { for (i, src) in op.srcs.iter().enumerate() {
let out_reg = u32::try_from(i).unwrap(); let out_reg = u32::try_from(i).unwrap();
if let Some(ssa) = src_ssa_ref(src) { if let Some(ssa) = src_ssa_ref(src) {
@@ -1130,7 +1130,7 @@ impl AssignRegsBlock {
Some(instr) Some(instr)
} }
} }
Op::FSOut(out) => { Op::RegOut(out) => {
for src in out.srcs.iter_mut() { for src in out.srcs.iter_mut() {
if let Some(src_vec) = src_ssa_ref(src) { if let Some(src_vec) = src_ssa_ref(src) {
debug_assert!(src_vec.comps() == 1); debug_assert!(src_vec.comps() == 1);

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@@ -2364,7 +2364,7 @@ impl<'a> ShaderFromNir<'a> {
} }
} }
b.push_op(OpFSOut { srcs: srcs }); b.push_op(OpRegOut { srcs: srcs });
} }
nir_intrinsic_demote => { nir_intrinsic_demote => {
if let ShaderStageInfo::Fragment(info) = &mut self.info.stage { if let ShaderStageInfo::Fragment(info) = &mut self.info.stage {

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@@ -5974,11 +5974,11 @@ impl_display_for_op!(OpParCopy);
#[repr(C)] #[repr(C)]
#[derive(DstsAsSlice)] #[derive(DstsAsSlice)]
pub struct OpFSOut { pub struct OpRegOut {
pub srcs: Vec<Src>, pub srcs: Vec<Src>,
} }
impl SrcsAsSlice for OpFSOut { impl SrcsAsSlice for OpRegOut {
fn srcs_as_slice(&self) -> &[Src] { fn srcs_as_slice(&self) -> &[Src] {
&self.srcs &self.srcs
} }
@@ -5992,9 +5992,9 @@ impl SrcsAsSlice for OpFSOut {
} }
} }
impl DisplayOp for OpFSOut { impl DisplayOp for OpRegOut {
fn fmt_op(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { fn fmt_op(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
write!(f, "fs_out {{")?; write!(f, "reg_out {{")?;
for (i, src) in self.srcs.iter().enumerate() { for (i, src) in self.srcs.iter().enumerate() {
if i > 0 { if i > 0 {
write!(f, ",")?; write!(f, ",")?;
@@ -6004,7 +6004,7 @@ impl DisplayOp for OpFSOut {
write!(f, " }}") write!(f, " }}")
} }
} }
impl_display_for_op!(OpFSOut); impl_display_for_op!(OpRegOut);
#[derive(Copy, Clone, Debug, PartialEq)] #[derive(Copy, Clone, Debug, PartialEq)]
pub enum OutType { pub enum OutType {
@@ -6184,7 +6184,7 @@ pub enum Op {
Unpin(OpUnpin), Unpin(OpUnpin),
Swap(OpSwap), Swap(OpSwap),
ParCopy(OpParCopy), ParCopy(OpParCopy),
FSOut(OpFSOut), RegOut(OpRegOut),
Out(OpOut), Out(OpOut),
OutFinal(OpOutFinal), OutFinal(OpOutFinal),
Annotate(OpAnnotate), Annotate(OpAnnotate),
@@ -6550,7 +6550,7 @@ impl Instr {
| Op::Exit(_) | Op::Exit(_)
| Op::WarpSync(_) | Op::WarpSync(_)
| Op::Bar(_) | Op::Bar(_)
| Op::FSOut(_) | Op::RegOut(_)
| Op::Out(_) | Op::Out(_)
| Op::OutFinal(_) | Op::OutFinal(_)
| Op::Annotate(_) => false, | Op::Annotate(_) => false,
@@ -6687,7 +6687,7 @@ impl Instr {
| Op::Unpin(_) | Op::Unpin(_)
| Op::Swap(_) | Op::Swap(_)
| Op::ParCopy(_) | Op::ParCopy(_)
| Op::FSOut(_) | Op::RegOut(_)
| Op::Annotate(_) => { | Op::Annotate(_) => {
panic!("Not a hardware opcode") panic!("Not a hardware opcode")
} }

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@@ -298,7 +298,7 @@ fn legalize_instr(
| Op::PhiDsts(_) | Op::PhiDsts(_)
| Op::Pin(_) | Op::Pin(_)
| Op::Unpin(_) | Op::Unpin(_)
| Op::FSOut(_) => { | Op::RegOut(_) => {
// These are implemented by RA and can take pretty much anything // These are implemented by RA and can take pretty much anything
// you can throw at them. // you can throw at them.
debug_assert!(instr.pred.is_true()); debug_assert!(instr.pred.is_true());

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@@ -209,11 +209,11 @@ pub trait Liveness {
max(max_live[file], live_at_instr[file]) max(max_live[file], live_at_instr[file])
}); });
if let Op::FSOut(fs_out) = &instr.op { if let Op::RegOut(reg_out) = &instr.op {
// This should be the last instruction. Everything should // This should be the last instruction. Everything should
// be dead once we've processed it. // be dead once we've processed it.
debug_assert!(live.count(RegFile::GPR) == 0); debug_assert!(live.count(RegFile::GPR) == 0);
let num_gprs_out = fs_out.srcs.len().try_into().unwrap(); let num_gprs_out = reg_out.srcs.len().try_into().unwrap();
max_live[RegFile::GPR] = max_live[RegFile::GPR] =
max(max_live[RegFile::GPR], num_gprs_out); max(max_live[RegFile::GPR], num_gprs_out);
} }