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intel/fs: Rename half() helpers to quarter(), allow index up to 3.

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Makes more sense considering SIMD32.  Relaxing the assertion in
brw_ir_fs.h will be required in order to avoid assertion failures on
SNB with SIMD32 fragment shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez
2020-04-03 13:04:43 -07:00
parent bdad7f429a
commit 6310a05f68
4 changed files with 14 additions and 14 deletions
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6
src/intel/compiler/brw_fs.cpp
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@@ -208,7 +208,7 @@ fs_visitor::DEP_RESOLVE_MOV(const fs_builder &bld, int grf)
* dependencies, and to avoid having to deal with aligning its regs to 2. * dependencies, and to avoid having to deal with aligning its regs to 2.
*/ */
const fs_builder ubld = bld.annotate("send dependency resolve") const fs_builder ubld = bld.annotate("send dependency resolve")
.half(0); .quarter(0);
ubld.MOV(ubld.null_reg_f(), fs_reg(VGRF, grf, BRW_REGISTER_TYPE_F)); ubld.MOV(ubld.null_reg_f(), fs_reg(VGRF, grf, BRW_REGISTER_TYPE_F));
} }
@@ -3885,9 +3885,9 @@ fs_visitor::lower_load_payload()
} else { } else {
/* Platform doesn't have COMPR4. We have to fake it */ /* Platform doesn't have COMPR4. We have to fake it */
fs_reg mov_dst = retype(dst, inst->src[i].type); fs_reg mov_dst = retype(dst, inst->src[i].type);
ibld.half(0).MOV(mov_dst, half(inst->src[i], 0)); ibld.quarter(0).MOV(mov_dst, quarter(inst->src[i], 0));
mov_dst.nr += 4; mov_dst.nr += 4;
ibld.half(1).MOV(mov_dst, half(inst->src[i], 1)); ibld.quarter(1).MOV(mov_dst, quarter(inst->src[i], 1));
} }
} }

2
src/intel/compiler/brw_fs_builder.h
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@@ -140,7 +140,7 @@ namespace brw {
* Alias for group() with width equal to eight. * Alias for group() with width equal to eight.
*/ */
fs_builder fs_builder
half(unsigned i) const quarter(unsigned i) const
{ {
return group(8, i); return group(8, i);
} }

15
src/intel/compiler/brw_fs_visitor.cpp
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@@ -179,10 +179,10 @@ fs_visitor::emit_interpolation_setup_gen4()
if (devinfo->has_pln) { if (devinfo->has_pln) {
for (unsigned i = 0; i < dispatch_width / 8; i++) { for (unsigned i = 0; i < dispatch_width / 8; i++) {
abld.half(i).ADD(half(offset(delta_xy, abld, 0), i), abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 0), i),
half(this->pixel_x, i), xstart); quarter(this->pixel_x, i), xstart);
abld.half(i).ADD(half(offset(delta_xy, abld, 1), i), abld.quarter(i).ADD(quarter(offset(delta_xy, abld, 1), i),
half(this->pixel_y, i), ystart); quarter(this->pixel_y, i), ystart);
} }
} else { } else {
abld.ADD(offset(delta_xy, abld, 0), this->pixel_x, xstart); abld.ADD(offset(delta_xy, abld, 0), this->pixel_x, xstart);
@@ -360,9 +360,10 @@ fs_visitor::emit_interpolation_setup_gen6()
for (unsigned c = 0; c < 2; c++) { for (unsigned c = 0; c < 2; c++) {
for (unsigned q = 0; q < dispatch_width / 8; q++) { for (unsigned q = 0; q < dispatch_width / 8; q++) {
set_predicate(BRW_PREDICATE_NORMAL, set_predicate(BRW_PREDICATE_NORMAL,
bld.half(q).SEL(half(offset(delta_xy[i], bld, c), q), bld.quarter(q).SEL(
half(offset(centroid_delta_xy, bld, c), q), quarter(offset(delta_xy[i], bld, c), q),
half(offset(pixel_delta_xy, bld, c), q))); quarter(offset(centroid_delta_xy, bld, c), q),
quarter(offset(pixel_delta_xy, bld, c), q)));
} }
} }
} }

5
src/intel/compiler/brw_ir_fs.h
View File

@@ -276,12 +276,11 @@ is_uniform(const fs_reg &reg)
/** /**
* Get the specified 8-component quarter of a register. * Get the specified 8-component quarter of a register.
* XXX - Maybe come up with a less misleading name for this (e.g. quarter())?
*/ */
static inline fs_reg static inline fs_reg
half(const fs_reg &reg, unsigned idx) quarter(const fs_reg &reg, unsigned idx)
{ {
assert(idx < 2); assert(idx < 4);
return horiz_offset(reg, 8 * idx); return horiz_offset(reg, 8 * idx);
} }