From 62a25f064917c701764e7d7063fd924b1facee15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Wed, 27 Mar 2024 09:22:48 -0700 Subject: [PATCH] anv/xe2: Add STATE_COMPUTE_MODE individual masks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So we can enable each mask individually when programming registers. Also setting Mask2/mask of the second double word so all registers in it are also zeored during state init. Reviewed-by: Lionel Landwerlin Signed-off-by: José Roberto de Souza Part-of: --- src/intel/genxml/gen20.xml | 10 ++++++++++ src/intel/vulkan/genX_init_state.c | 3 +++ 2 files changed, 13 insertions(+) diff --git a/src/intel/genxml/gen20.xml b/src/intel/genxml/gen20.xml index 7308301c134..41a58a69e13 100644 --- a/src/intel/genxml/gen20.xml +++ b/src/intel/genxml/gen20.xml @@ -1061,7 +1061,12 @@ + + + + + @@ -1086,7 +1091,12 @@ + + + + + diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c index 4938e5b6621..bdfc95fd0d8 100644 --- a/src/intel/vulkan/genX_init_state.c +++ b/src/intel/vulkan/genX_init_state.c @@ -589,6 +589,9 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch) #if GFX_VERx10 >= 125 anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), cm) { cm.Mask1 = 0xffff; +#if GFX_VERx10 >= 200 + cm.Mask2 = 0xffff; +#endif } anv_batch_emit(&batch, GENX(3DSTATE_MESH_CONTROL), zero); anv_batch_emit(&batch, GENX(3DSTATE_TASK_CONTROL), zero);