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anv/xe2: Add STATE_COMPUTE_MODE individual masks

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So we can enable each mask individually when programming registers.
Also setting Mask2/mask of the second double word so all registers in
it are also zeored during state init.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29616>
This commit is contained in:
José Roberto de Souza
2024-03-27 09:22:48 -07:00
committed by Marge Bot
parent a472d415bc
commit 62a25f0649
2 changed files with 13 additions and 0 deletions
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10
src/intel/genxml/gen20.xml
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@@ -1061,7 +1061,12 @@
</field>
<field name="EU Thread Scheduling Mode Override" start="45" end="46" type="uint" />
<field name="Large GRF Mode" start="47" end="47" type="bool" />
<field name="Z Pass Async Compute Thread Limit Mask" start="48" end="50" type="uint" />
<field name="Mask1" start="48" end="63" type="uint" />
<field name="Z Async Throttle settings Mask" start="51" end="52" type="uint" />
<field name="Pixel Async Compute Thread Limit Mask" start="55" end="57" type="uint" />
<field name="EU Thread Scheduling Mode Override Mask" start="61" end="62" type="uint" />
<field name="Large GRF Mode Mask" start="63" end="63" type="bool" />
<field name="Midthread Preemption Delay Timer" start="64" end="66" type="uint">
<value name="MTP_TIMER_VAL_0" value="0" />
<value name="MTP_TIMER_VAL_50" value="1" />
@@ -1086,7 +1091,12 @@
<value name="Full" value="0" />
<value name="Min" value="1" />
</field>
<field name="Midthread Preemption Delay Timer Mask" start="80" end="82" type="uint" />
<field name="Mask2" start="80" end="95" type="uint" />
<field name="Midthread Preemption Overdispatch Thread group count Mask" start="83" end="84" type="uint" />
<field name="Midthread Preemption Overdispatch Test mode Mask" start="85" end="85" type="uint" />
<field name="UAV Coherency Mode Mask" start="86" end="86" type="uint" />
<field name="Memory allocation for Scratch and Midthread Preemption buffers Mask" start="91" end="91" type="uint" />
</instruction>
<instruction name="XY_BLOCK_COPY_BLT" bias="2" length="22" engine="blitter">
<field name="DWord Length" start="0" end="7" type="uint" default="20" />

3
src/intel/vulkan/genX_init_state.c
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@@ -589,6 +589,9 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
#if GFX_VERx10 >= 125
anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), cm) {
cm.Mask1 = 0xffff;
#if GFX_VERx10 >= 200
cm.Mask2 = 0xffff;
#endif
}
anv_batch_emit(&batch, GENX(3DSTATE_MESH_CONTROL), zero);
anv_batch_emit(&batch, GENX(3DSTATE_TASK_CONTROL), zero);