diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index e4b837c561c..367524c5e38 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -385,7 +385,7 @@ type_size(const struct glsl_type *type, bool bindless)
 bool
 mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
                        unsigned bit_size,
-                       unsigned num_components, unsigned high_offset,
+                       unsigned num_components,
                        nir_intrinsic_instr *low, nir_intrinsic_instr *high)
 {
    if (num_components > 4)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 80d89b7f3f2..5ac625904b9 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -4854,7 +4854,7 @@ bool nir_opt_conditional_discard(nir_shader *shader);
 typedef bool (*nir_should_vectorize_mem_func)(unsigned align_mul,
                                               unsigned align_offset,
                                               unsigned bit_size,
-                                              unsigned num_components, unsigned high_offset,
+                                              unsigned num_components,
                                               nir_intrinsic_instr *low, nir_intrinsic_instr *high);
 
 bool nir_opt_load_store_vectorize(nir_shader *shader, nir_variable_mode modes,
diff --git a/src/compiler/nir/nir_opt_load_store_vectorize.c b/src/compiler/nir/nir_opt_load_store_vectorize.c
index 6ae69031820..51405fa1bc3 100644
--- a/src/compiler/nir/nir_opt_load_store_vectorize.c
+++ b/src/compiler/nir/nir_opt_load_store_vectorize.c
@@ -670,7 +670,7 @@ new_bitsize_acceptable(struct vectorize_ctx *ctx, unsigned new_bit_size,
    if (!ctx->callback(low->align_mul,
                       low->align_offset,
                       new_bit_size, new_num_components,
-                      high_offset, low->intrin, high->intrin))
+                      low->intrin, high->intrin))
       return false;
 
    if (low->is_store) {
diff --git a/src/compiler/nir/tests/load_store_vectorizer_tests.cpp b/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
index dd9d4015836..0f49d30e01a 100644
--- a/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
+++ b/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
@@ -72,7 +72,7 @@ protected:
 
    static bool mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
                                       unsigned bit_size,
-                                      unsigned num_components, unsigned high_offset,
+                                      unsigned num_components,
                                       nir_intrinsic_instr *low, nir_intrinsic_instr *high);
    static void shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align);
 
@@ -365,7 +365,7 @@ bool nir_load_store_vectorize_test::test_alu_def(
 
 bool nir_load_store_vectorize_test::mem_vectorize_callback(
    unsigned align_mul, unsigned align_offset, unsigned bit_size,
-   unsigned num_components, unsigned high_offset,
+   unsigned num_components,
    nir_intrinsic_instr *low, nir_intrinsic_instr *high)
 {
    return bit_size / 8;
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index c1af534295f..0de36e67984 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -857,7 +857,7 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
 static bool
 brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
                              unsigned bit_size,
-                             unsigned num_components, unsigned high_offset,
+                             unsigned num_components,
                              nir_intrinsic_instr *low,
                              nir_intrinsic_instr *high)
 {