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radv: do not need to force emit the TCS regs on Vega20

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This chip doesn't need the fixup. This fixes a bunch of
dEQP-VK.tessellation tests and avoid random GPU hangs.

Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2019-05-01 16:10:44 +02:00
parent bf774b56be
commit 6162543999
1 changed files with 1 additions and 0 deletions
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src/amd/vulkan/radv_nir_to_llvm.c
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@@ -3691,6 +3691,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
ac_init_exec_full_mask(&ctx.ac); ac_init_exec_full_mask(&ctx.ac);
if (ctx.ac.chip_class == GFX9 && if (ctx.ac.chip_class == GFX9 &&
ctx.ac.family != CHIP_VEGA20 &&
shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL) shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
ac_nir_fixup_ls_hs_input_vgprs(&ctx); ac_nir_fixup_ls_hs_input_vgprs(&ctx);