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intel/fs/xe2+: Fix payload layout of sampler messages for Xe2 reg size

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Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Francisco Jerez
2022-08-24 11:46:45 -07:00
committed by Jordan Justen
parent c9f2857546
commit 610daa3166
1 changed files with 5 additions and 5 deletions
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10
src/intel/compiler/brw_lower_logical_sends.cpp
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@@ -823,7 +823,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_D); brw_reg_type_from_bit_size(payload_type_bit_size, BRW_REGISTER_TYPE_D);
unsigned reg_width = bld.dispatch_width() / 8; unsigned reg_width = bld.dispatch_width() / 8;
unsigned header_size = 0, length = 0; unsigned header_size = 0, length = 0;
fs_reg sources[MAX_SAMPLER_MESSAGE_SIZE]; fs_reg sources[1 + MAX_SAMPLER_MESSAGE_SIZE];
for (unsigned i = 0; i < ARRAY_SIZE(sources); i++) for (unsigned i = 0; i < ARRAY_SIZE(sources); i++)
sources[i] = bld.vgrf(payload_type); sources[i] = bld.vgrf(payload_type);
@@ -846,8 +846,8 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
* the header. * the header.
*/ */
fs_reg header = retype(sources[0], BRW_REGISTER_TYPE_UD); fs_reg header = retype(sources[0], BRW_REGISTER_TYPE_UD);
header_size = 1; for (header_size = 0; header_size < reg_unit(devinfo); header_size++)
length++; sources[length++] = byte_offset(header, REG_SIZE * header_size);
/* If we're requesting fewer than four channels worth of response, /* If we're requesting fewer than four channels worth of response,
* and we have an explicit header, we need to set up the sampler * and we have an explicit header, we need to set up the sampler
@@ -864,7 +864,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
inst->offset |= 1 << 23; /* g0.2 bit23 : Pixel Null Mask Enable */ inst->offset |= 1 << 23; /* g0.2 bit23 : Pixel Null Mask Enable */
/* Build the actual header */ /* Build the actual header */
const fs_builder ubld = bld.exec_all().group(8, 0); const fs_builder ubld = bld.exec_all().group(8 * reg_unit(devinfo), 0);
const fs_builder ubld1 = ubld.group(1, 0); const fs_builder ubld1 = ubld.group(1, 0);
ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
if (inst->offset) { if (inst->offset) {
@@ -1133,7 +1133,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
*/ */
fs_inst *load_payload_inst = fs_inst *load_payload_inst =
emit_load_payload_with_padding(bld, src_payload, sources, length, emit_load_payload_with_padding(bld, src_payload, sources, length,
header_size, REG_SIZE); header_size, REG_SIZE * reg_unit(devinfo));
unsigned mlen = load_payload_inst->size_written / REG_SIZE; unsigned mlen = load_payload_inst->size_written / REG_SIZE;
unsigned simd_mode = 0; unsigned simd_mode = 0;
if (payload_type_bit_size == 16) { if (payload_type_bit_size == 16) {