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radv/meta: rework creating DCC retile pipelines

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30233>
This commit is contained in:
Samuel Pitoiset
2024-07-17 22:27:04 +02:00
committed by Marge Bot
parent 176befe439
commit 602bdda3a5
1 changed files with 36 additions and 23 deletions
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59
src/amd/vulkan/meta/radv_meta_dcc_retile.c
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@@ -84,10 +84,9 @@ radv_device_finish_meta_dcc_retile_state(struct radv_device *device)
* BPE is always 4 at the moment and the rest is derived from the tilemode. * BPE is always 4 at the moment and the rest is derived from the tilemode.
*/ */
static VkResult static VkResult
radv_device_init_meta_dcc_retile_state(struct radv_device *device, struct radeon_surf *surf) create_pipeline(struct radv_device *device, struct radeon_surf *surf)
{ {
VkResult result = VK_SUCCESS; VkResult result = VK_SUCCESS;
nir_shader *cs = build_dcc_retile_compute_shader(device, surf);
if (!device->meta_state.dcc_retile.ds_layout) { if (!device->meta_state.dcc_retile.ds_layout) {
const VkDescriptorSetLayoutBinding bindings[] = { const VkDescriptorSetLayoutBinding bindings[] = {
@@ -108,7 +107,7 @@ radv_device_init_meta_dcc_retile_state(struct radv_device *device, struct radeon
result = radv_meta_create_descriptor_set_layout(device, 2, bindings, &device->meta_state.dcc_retile.ds_layout); result = radv_meta_create_descriptor_set_layout(device, 2, bindings, &device->meta_state.dcc_retile.ds_layout);
if (result != VK_SUCCESS) if (result != VK_SUCCESS)
goto cleanup; return result;
} }
if (!device->meta_state.dcc_retile.p_layout) { if (!device->meta_state.dcc_retile.p_layout) {
@@ -120,53 +119,67 @@ radv_device_init_meta_dcc_retile_state(struct radv_device *device, struct radeon
result = radv_meta_create_pipeline_layout(device, &device->meta_state.dcc_retile.ds_layout, 1, &pc_range, result = radv_meta_create_pipeline_layout(device, &device->meta_state.dcc_retile.ds_layout, 1, &pc_range,
&device->meta_state.dcc_retile.p_layout); &device->meta_state.dcc_retile.p_layout);
if (result != VK_SUCCESS) if (result != VK_SUCCESS)
goto cleanup; return result;
} }
nir_shader *cs = build_dcc_retile_compute_shader(device, surf);
result = radv_meta_create_compute_pipeline(device, cs, device->meta_state.dcc_retile.p_layout, result = radv_meta_create_compute_pipeline(device, cs, device->meta_state.dcc_retile.p_layout,
&device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]); &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]);
if (result != VK_SUCCESS)
goto cleanup;
cleanup:
ralloc_free(cs); ralloc_free(cs);
return result; return result;
} }
static VkResult
get_pipeline(struct radv_device *device, struct radv_image *image, VkPipeline *pipeline_out)
{
struct radv_meta_state *state = &device->meta_state;
VkResult result = VK_SUCCESS;
const unsigned swizzle_mode = image->planes[0].surface.u.gfx9.swizzle_mode;
mtx_lock(&state->mtx);
if (!state->dcc_retile.pipeline[swizzle_mode]) {
result = create_pipeline(device, &image->planes[0].surface);
if (result != VK_SUCCESS)
goto fail;
}
*pipeline_out = state->dcc_retile.pipeline[swizzle_mode];
fail:
mtx_unlock(&state->mtx);
return result;
}
void void
radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image) radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
{ {
struct radv_meta_saved_state saved_state; struct radv_meta_saved_state saved_state;
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radv_buffer buffer; struct radv_buffer buffer;
VkPipeline pipeline;
VkResult result;
assert(image->vk.image_type == VK_IMAGE_TYPE_2D); assert(image->vk.image_type == VK_IMAGE_TYPE_2D);
assert(image->vk.array_layers == 1 && image->vk.mip_levels == 1); assert(image->vk.array_layers == 1 && image->vk.mip_levels == 1);
struct radv_cmd_state *state = &cmd_buffer->state; struct radv_cmd_state *state = &cmd_buffer->state;
result = get_pipeline(device, image, &pipeline);
if (result != VK_SUCCESS) {
vk_command_buffer_set_error(&cmd_buffer->vk, result);
return;
}
state->flush_bits |= state->flush_bits |=
radv_dst_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT, VK_ACCESS_2_SHADER_READ_BIT, image); radv_dst_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT, VK_ACCESS_2_SHADER_READ_BIT, image);
unsigned swizzle_mode = image->planes[0].surface.u.gfx9.swizzle_mode;
/* Compile pipelines if not already done so. */
mtx_lock(&device->meta_state.mtx);
if (!device->meta_state.dcc_retile.pipeline[swizzle_mode]) {
VkResult ret = radv_device_init_meta_dcc_retile_state(device, &image->planes[0].surface);
if (ret != VK_SUCCESS) {
mtx_unlock(&device->meta_state.mtx);
vk_command_buffer_set_error(&cmd_buffer->vk, ret);
return;
}
}
mtx_unlock(&device->meta_state.mtx);
radv_meta_save(&saved_state, cmd_buffer, radv_meta_save(&saved_state, cmd_buffer,
RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS); RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
device->meta_state.dcc_retile.pipeline[swizzle_mode]);
radv_buffer_init(&buffer, device, image->bindings[0].bo, image->size, image->bindings[0].offset); radv_buffer_init(&buffer, device, image->bindings[0].bo, image->size, image->bindings[0].offset);