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gallium/radeon: remove rcs parameter from radeon_winsys::buffer_set_tiling

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This was needed for DRM < 2.12.0 where the kernel was rewriting tiling flags
in IBs.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2016-02-24 00:58:38 +01:00
parent 260ef9c9be
commit 6011d7cf25
5 changed files with 2 additions and 13 deletions
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2
src/gallium/drivers/r300/r300_texture.c
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@@ -1064,7 +1064,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
tiling.microtile = tex->tex.microtile; tiling.microtile = tex->tex.microtile;
tiling.macrotile = tex->tex.macrotile[0]; tiling.macrotile = tex->tex.macrotile[0];
tiling.stride = tex->tex.stride_in_bytes[0]; tiling.stride = tex->tex.stride_in_bytes[0];
rws->buffer_set_tiling(tex->buf, NULL, &tiling); rws->buffer_set_tiling(tex->buf, &tiling);
return tex; return tex;

2
src/gallium/drivers/radeon/r600_texture.c
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@@ -253,7 +253,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
metadata.stride = surface->level[0].pitch_bytes; metadata.stride = surface->level[0].pitch_bytes;
metadata.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0; metadata.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
rscreen->ws->buffer_set_tiling(resource->buf, NULL, &metadata); rscreen->ws->buffer_set_tiling(resource->buf, &metadata);
return rscreen->ws->buffer_get_handle(resource->buf, return rscreen->ws->buffer_get_handle(resource->buf,
surface->level[0].pitch_bytes, whandle); surface->level[0].pitch_bytes, whandle);

2
src/gallium/drivers/radeon/radeon_winsys.h
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@@ -483,11 +483,9 @@ struct radeon_winsys {
* (tiling info for display code, DRI sharing, and other data) * (tiling info for display code, DRI sharing, and other data)
* *
* \param buf A winsys buffer object to set the flags for. * \param buf A winsys buffer object to set the flags for.
* \param cs A command stream to flush if the buffer is referenced by it.
* \param md Metadata * \param md Metadata
*/ */
void (*buffer_set_tiling)(struct pb_buffer *buf, void (*buffer_set_tiling)(struct pb_buffer *buf,
struct radeon_winsys_cs *rcs,
struct radeon_bo_metadata *md); struct radeon_bo_metadata *md);
/** /**

1
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
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@@ -420,7 +420,6 @@ static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
} }
static void amdgpu_bo_set_tiling(struct pb_buffer *_buf, static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
struct radeon_winsys_cs *rcs,
struct radeon_bo_metadata *md) struct radeon_bo_metadata *md)
{ {
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);

8
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
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@@ -671,21 +671,13 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf,
} }
static void radeon_bo_set_tiling(struct pb_buffer *_buf, static void radeon_bo_set_tiling(struct pb_buffer *_buf,
struct radeon_winsys_cs *rcs,
struct radeon_bo_metadata *md) struct radeon_bo_metadata *md)
{ {
struct radeon_bo *bo = radeon_bo(_buf); struct radeon_bo *bo = radeon_bo(_buf);
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct drm_radeon_gem_set_tiling args; struct drm_radeon_gem_set_tiling args;
memset(&args, 0, sizeof(args)); memset(&args, 0, sizeof(args));
/* Tiling determines how DRM treats the buffer data.
* We must flush CS when changing it if the buffer is referenced. */
if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
cs->flush_cs(cs->flush_data, 0, NULL);
}
os_wait_until_zero(&bo->num_active_ioctls, PIPE_TIMEOUT_INFINITE); os_wait_until_zero(&bo->num_active_ioctls, PIPE_TIMEOUT_INFINITE);
if (md->microtile == RADEON_LAYOUT_TILED) if (md->microtile == RADEON_LAYOUT_TILED)