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nir: Make the load_store_vectorizer provide align_mul + align_offset.

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It was passing an encoding of the two that wasn't good for ensuring "Don't
combine loads that would make us straddle a vec4 boundary" for
nir_lower_ubo_vec4.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6612>
This commit is contained in:
Eric Anholt
2020-09-08 10:58:49 -07:00
committed by Marge Bot
parent 9c5a793dc7
commit 5f757bb95c
5 changed files with 27 additions and 7 deletions
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10
src/intel/compiler/brw_nir.c
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@@ -855,7 +855,8 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
}
static bool
brw_nir_should_vectorize_mem(unsigned align, unsigned bit_size,
brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
unsigned bit_size,
unsigned num_components, unsigned high_offset,
nir_intrinsic_instr *low,
nir_intrinsic_instr *high)
@@ -873,6 +874,13 @@ brw_nir_should_vectorize_mem(unsigned align, unsigned bit_size,
if (num_components > 4)
return false;
uint32_t align;
if (align_offset)
align = 1 << (ffs(align_offset) - 1);
else
align = align_mul;
if (align < bit_size / 8)
return false;