i965: Add functions to abstract access to 3src register types
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
This commit is contained in:
@@ -736,26 +736,8 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
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* may send us mixed D and UD types and want us to ignore that and use
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* may send us mixed D and UD types and want us to ignore that and use
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* the destination type.
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* the destination type.
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*/
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*/
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switch (dest.type) {
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brw_inst_set_3src_a16_src_type(devinfo, inst, dest.type);
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case BRW_REGISTER_TYPE_F:
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brw_inst_set_3src_a16_dst_type(devinfo, inst, dest.type);
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brw_inst_set_3src_a16_src_hw_type(devinfo, inst, BRW_3SRC_TYPE_F);
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brw_inst_set_3src_a16_dst_hw_type(devinfo, inst, BRW_3SRC_TYPE_F);
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break;
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case BRW_REGISTER_TYPE_DF:
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brw_inst_set_3src_a16_src_hw_type(devinfo, inst, BRW_3SRC_TYPE_DF);
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brw_inst_set_3src_a16_dst_hw_type(devinfo, inst, BRW_3SRC_TYPE_DF);
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break;
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case BRW_REGISTER_TYPE_D:
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brw_inst_set_3src_a16_src_hw_type(devinfo, inst, BRW_3SRC_TYPE_D);
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brw_inst_set_3src_a16_dst_hw_type(devinfo, inst, BRW_3SRC_TYPE_D);
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break;
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case BRW_REGISTER_TYPE_UD:
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brw_inst_set_3src_a16_src_hw_type(devinfo, inst, BRW_3SRC_TYPE_UD);
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brw_inst_set_3src_a16_dst_hw_type(devinfo, inst, BRW_3SRC_TYPE_UD);
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break;
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default:
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unreachable("not reached");
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}
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}
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}
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return inst;
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return inst;
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@@ -246,6 +246,27 @@ F(3src_access_mode, 8, 8)
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F(3src_opcode, 6, 0)
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F(3src_opcode, 6, 0)
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/** @} */
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/** @} */
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#define REG_TYPE(reg) \
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static inline void \
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brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
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brw_inst *inst, enum brw_reg_type type) \
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{ \
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unsigned hw_type = brw_reg_type_to_hw_3src_type(devinfo, type); \
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brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
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} \
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\
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static inline enum brw_reg_type \
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brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
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const brw_inst *inst) \
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{ \
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unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
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return brw_hw_3src_type_to_reg_type(devinfo, hw_type); \
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}
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REG_TYPE(dst)
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REG_TYPE(src)
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#undef REG_TYPE
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/**
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/**
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* Flow control instruction bits:
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* Flow control instruction bits:
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* @{
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* @{
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