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Revert "ac/gpu_info: pad IBs according to ib_size_alignment"

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This reverts commit 4f660f9937.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25558>
This commit is contained in:
Marek Olšák
2023-10-05 04:52:24 -04:00
committed by Marge Bot
parent 29f9c49228
commit 5f42a21dad
1 changed files with 13 additions and 13 deletions
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26
src/amd/common/ac_gpu_info.c
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@@ -676,20 +676,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
device_info.family == FAMILY_MDN)
info->ip[AMD_IP_GFX].ver_minor = info->ip[AMD_IP_COMPUTE].ver_minor = 3;
}
info->ip[ip_type].num_queues = util_bitcount(ip_info.available_rings);
info->ip[ip_type].ib_base_alignment = ip_info.ib_start_alignment;
info->ip[ip_type].ib_size_alignment = ip_info.ib_size_alignment;
/* I guess we must align IBs due to caching on GFX9. This fixes a hang. */
if ((ip_type == AMD_IP_GFX || ip_type == AMD_IP_COMPUTE) &&
info->ip[ip_type].ver_major == 9) {
info->ip[ip_type].ib_base_alignment = MAX2(info->ip[ip_type].ib_base_alignment, 64);
info->ip[ip_type].ib_size_alignment = MAX2(info->ip[ip_type].ib_size_alignment, 64);
}
info->ib_pad_dw_mask[ip_type] = info->ip[ip_type].ib_size_alignment > 4 ?
info->ip[ip_type].ib_size_alignment / 4 - 1 : 0;
}
/* Only require gfx or compute. */
@@ -1137,6 +1126,17 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->lds_encode_granularity = info->gfx_level >= GFX7 ? 128 * 4 : 64 * 4;
info->lds_alloc_granularity = info->gfx_level >= GFX10_3 ? 256 * 4 : info->lds_encode_granularity;
/* This is "align_mask" copied from the kernel, maximums of all IP versions. */
info->ib_pad_dw_mask[AMD_IP_GFX] = 0xff;
info->ib_pad_dw_mask[AMD_IP_COMPUTE] = 0xff;
info->ib_pad_dw_mask[AMD_IP_SDMA] = 0xf;
info->ib_pad_dw_mask[AMD_IP_UVD] = 0xf;
info->ib_pad_dw_mask[AMD_IP_VCE] = 0x3f;
info->ib_pad_dw_mask[AMD_IP_UVD_ENC] = 0x3f;
info->ib_pad_dw_mask[AMD_IP_VCN_DEC] = 0xf;
info->ib_pad_dw_mask[AMD_IP_VCN_ENC] = 0x3f;
info->ib_pad_dw_mask[AMD_IP_VCN_JPEG] = 0xf;
/* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
* on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
* SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
@@ -1676,10 +1676,10 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
for (unsigned i = 0; i < AMD_NUM_IP_TYPES; i++) {
if (info->ip[i].num_queues) {
fprintf(f, " IP %-7s %2u.%u queues:%u "
"align(base:%u, size:%u, dw_mask:0x%x)\n",
"align(base:%u, size:%u)\n",
ip_string[i], info->ip[i].ver_major, info->ip[i].ver_minor,
info->ip[i].num_queues, info->ip[i].ib_base_alignment,
info->ip[i].ib_size_alignment, info->ib_pad_dw_mask[i]);
info->ip[i].ib_size_alignment);
}
}