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compiler: Merge shader_info's tcs and tes structs.

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Annoyingly, SPIR-V lets you specify all of these fields in either the
TCS or TES, which means that we need to be able to store all of them
for either shader stage.  Putting them in a union won't work.

Combining both is an easy solution, and given that the TCS struct only
had a single field, it's pretty inexpensive.

This patch renames the combined struct to "tess" to indicate that it's
for tessellation in general, not one of the two stages.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Kenneth Graunke
2017-01-09 11:37:21 -08:00
parent 195bf8f027
commit 5edc338162
9 changed files with 37 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/compiler/shader_info.h
View File

@@ -142,18 +142,17 @@ typedef struct shader_info {
unsigned shared_size;
} cs;
/* Applies to both TCS and TES. */
struct {
/** The number of vertices in the TCS output patch. */
unsigned vertices_out;
} tcs;
unsigned tcs_vertices_out;
struct {
uint32_t primitive_mode; /* GL_TRIANGLES, GL_QUADS or GL_ISOLINES */
enum gl_tess_spacing spacing;
/** Is the vertex order counterclockwise? */
bool ccw;
bool point_mode;
} tes;
} tess;
};
} shader_info;

6
src/mesa/drivers/dri/i965/brw_fs.cpp
View File

@@ -5925,15 +5925,15 @@ fs_visitor::run_tcs_single_patch()
}
/* Fix the disptach mask */
if (nir->info->tcs.vertices_out % 8) {
if (nir->info->tess.tcs_vertices_out % 8) {
bld.CMP(bld.null_reg_ud(), invocation_id,
brw_imm_ud(nir->info->tcs.vertices_out), BRW_CONDITIONAL_L);
brw_imm_ud(nir->info->tess.tcs_vertices_out), BRW_CONDITIONAL_L);
bld.IF(BRW_PREDICATE_NORMAL);
}
emit_nir_code();
if (nir->info->tcs.vertices_out % 8) {
if (nir->info->tess.tcs_vertices_out % 8) {
bld.emit(BRW_OPCODE_ENDIF);
}

2
src/mesa/drivers/dri/i965/brw_nir.c
View File

@@ -336,7 +336,7 @@ brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue_map)
nir_builder_init(&b, function->impl);
nir_foreach_block(block, function->impl) {
remap_patch_urb_offsets(block, &b, vue_map,
nir->info->tes.primitive_mode);
nir->info->tess.primitive_mode);
}
}
}

10
src/mesa/drivers/dri/i965/brw_shader.cpp
View File

@@ -1351,9 +1351,9 @@ brw_compile_tes(const struct brw_compiler *compiler,
TESS_SPACING_FRACTIONAL_EVEN - 1);
prog_data->partitioning =
(enum brw_tess_partitioning) (nir->info->tes.spacing - 1);
(enum brw_tess_partitioning) (nir->info->tess.spacing - 1);
switch (nir->info->tes.primitive_mode) {
switch (nir->info->tess.primitive_mode) {
case GL_QUADS:
prog_data->domain = BRW_TESS_DOMAIN_QUAD;
break;
@@ -1367,14 +1367,14 @@ brw_compile_tes(const struct brw_compiler *compiler,
unreachable("invalid domain shader primitive mode");
}
if (nir->info->tes.point_mode) {
if (nir->info->tess.point_mode) {
prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
} else if (nir->info->tes.primitive_mode == GL_ISOLINES) {
} else if (nir->info->tess.primitive_mode == GL_ISOLINES) {
prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
} else {
/* Hardware winding order is backwards from OpenGL */
prog_data->output_topology =
nir->info->tes.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
nir->info->tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
: BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
}

8
src/mesa/drivers/dri/i965/brw_tcs.c
View File

@@ -54,7 +54,7 @@ create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler,
nir->info->inputs_read = key->outputs_written &
~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
nir->info->outputs_written = key->outputs_written;
nir->info->tcs.vertices_out = key->input_vertices;
nir->info->tess.tcs_vertices_out = key->input_vertices;
nir->info->name = ralloc_strdup(nir, "passthrough");
nir->num_uniforms = 8 * sizeof(uint32_t);
@@ -328,10 +328,10 @@ brw_tcs_populate_key(struct brw_context *brw,
/* We need to specialize our code generation for tessellation levels
* based on the domain the DS is expecting to tessellate.
*/
key->tes_primitive_mode = tep->program.info.tes.primitive_mode;
key->tes_primitive_mode = tep->program.info.tess.primitive_mode;
key->quads_workaround = brw->gen < 9 &&
tep->program.info.tes.primitive_mode == GL_QUADS &&
tep->program.info.tes.spacing == TESS_SPACING_EQUAL;
tep->program.info.tess.primitive_mode == GL_QUADS &&
tep->program.info.tess.spacing == TESS_SPACING_EQUAL;
if (tcp) {
key->program_string_id = tcp->id;

14
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
View File

@@ -94,9 +94,10 @@ vec4_tcs_visitor::emit_prolog()
* HS instance dispatched will only have its bottom half doing real
* work, and so we need to disable the upper half:
*/
if (nir->info->tcs.vertices_out % 2) {
if (nir->info->tess.tcs_vertices_out % 2) {
emit(CMP(dst_null_d(), invocation_id,
brw_imm_ud(nir->info->tcs.vertices_out), BRW_CONDITIONAL_L));
brw_imm_ud(nir->info->tess.tcs_vertices_out),
BRW_CONDITIONAL_L));
/* Matching ENDIF is in emit_thread_end() */
emit(IF(BRW_PREDICATE_NORMAL));
@@ -110,7 +111,7 @@ vec4_tcs_visitor::emit_thread_end()
vec4_instruction *inst;
current_annotation = "thread end";
if (nir->info->tcs.vertices_out % 2) {
if (nir->info->tess.tcs_vertices_out % 2) {
emit(BRW_OPCODE_ENDIF);
}
@@ -420,9 +421,9 @@ brw_compile_tcs(const struct brw_compiler *compiler,
nir = brw_postprocess_nir(nir, compiler, is_scalar);
if (is_scalar)
prog_data->instances = DIV_ROUND_UP(nir->info->tcs.vertices_out, 8);
prog_data->instances = DIV_ROUND_UP(nir->info->tess.tcs_vertices_out, 8);
else
prog_data->instances = DIV_ROUND_UP(nir->info->tcs.vertices_out, 2);
prog_data->instances = DIV_ROUND_UP(nir->info->tess.tcs_vertices_out, 2);
/* Compute URB entry size. The maximum allowed URB entry size is 32k.
* That divides up as follows:
@@ -441,7 +442,8 @@ brw_compile_tcs(const struct brw_compiler *compiler,
unsigned output_size_bytes = 0;
/* Note that the patch header is counted in num_per_patch_slots. */
output_size_bytes += num_per_patch_slots * 16;
output_size_bytes += nir->info->tcs.vertices_out * num_per_vertex_slots * 16;
output_size_bytes += nir->info->tess.tcs_vertices_out *
num_per_vertex_slots * 16;
assert(output_size_bytes >= 1);
if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)

10
src/mesa/main/shaderapi.c
View File

@@ -2183,14 +2183,14 @@ _mesa_copy_linked_program_data(const struct gl_shader_program *src,
dst->CullDistanceArraySize = src->Vert.CullDistanceArraySize;
break;
case MESA_SHADER_TESS_CTRL: {
dst->info.tcs.vertices_out = dst_sh->info.TessCtrl.VerticesOut;
dst->info.tess.tcs_vertices_out = dst_sh->info.TessCtrl.VerticesOut;
break;
}
case MESA_SHADER_TESS_EVAL: {
dst->info.tes.primitive_mode = dst_sh->info.TessEval.PrimitiveMode;
dst->info.tes.spacing = dst_sh->info.TessEval.Spacing;
dst->info.tes.ccw = dst_sh->info.TessEval.VertexOrder == GL_CCW;
dst->info.tes.point_mode = dst_sh->info.TessEval.PointMode;
dst->info.tess.primitive_mode = dst_sh->info.TessEval.PrimitiveMode;
dst->info.tess.spacing = dst_sh->info.TessEval.Spacing;
dst->info.tess.ccw = dst_sh->info.TessEval.VertexOrder == GL_CCW;
dst->info.tess.point_mode = dst_sh->info.TessEval.PointMode;
dst->ClipDistanceArraySize = src->TessEval.ClipDistanceArraySize;
dst->CullDistanceArraySize = src->TessEval.CullDistanceArraySize;
break;

2
src/mesa/program/prog_statevars.c
View File

@@ -610,7 +610,7 @@ _mesa_fetch_state(struct gl_context *ctx, const gl_state_index state[],
case STATE_TES_PATCH_VERTICES_IN:
if (ctx->TessCtrlProgram._Current)
val[0].i = ctx->TessCtrlProgram._Current->info.tcs.vertices_out;
val[0].i = ctx->TessCtrlProgram._Current->info.tess.tcs_vertices_out;
else
val[0].i = ctx->TessCtrlProgram.patch_vertices;
return;

12
src/mesa/state_tracker/st_program.c
View File

@@ -1577,7 +1577,7 @@ st_translate_tessctrl_program(struct st_context *st,
return false;
ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT,
sttcp->Base.info.tcs.vertices_out);
sttcp->Base.info.tess.tcs_vertices_out);
st_translate_program_common(st, &sttcp->Base, sttcp->glsl_to_tgsi, ureg,
PIPE_SHADER_TESS_CTRL, &sttcp->tgsi);
@@ -1601,11 +1601,11 @@ st_translate_tesseval_program(struct st_context *st,
if (ureg == NULL)
return false;
if (sttep->Base.info.tes.primitive_mode == GL_ISOLINES)
if (sttep->Base.info.tess.primitive_mode == GL_ISOLINES)
ureg_property(ureg, TGSI_PROPERTY_TES_PRIM_MODE, GL_LINES);
else
ureg_property(ureg, TGSI_PROPERTY_TES_PRIM_MODE,
sttep->Base.info.tes.primitive_mode);
sttep->Base.info.tess.primitive_mode);
STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
@@ -1614,12 +1614,12 @@ st_translate_tesseval_program(struct st_context *st,
PIPE_TESS_SPACING_FRACTIONAL_EVEN);
ureg_property(ureg, TGSI_PROPERTY_TES_SPACING,
(sttep->Base.info.tes.spacing + 1) % 3);
(sttep->Base.info.tess.spacing + 1) % 3);
ureg_property(ureg, TGSI_PROPERTY_TES_VERTEX_ORDER_CW,
!sttep->Base.info.tes.ccw);
!sttep->Base.info.tess.ccw);
ureg_property(ureg, TGSI_PROPERTY_TES_POINT_MODE,
sttep->Base.info.tes.point_mode);
sttep->Base.info.tess.point_mode);
st_translate_program_common(st, &sttep->Base, sttep->glsl_to_tgsi,
ureg, PIPE_SHADER_TESS_EVAL, &sttep->tgsi);