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i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators.

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We're going to use fs_generator/vec4_generator for Gen8+ code soon,
thanks to the new brw_instruction API.  When we do, we'll generally
want to take the Haswell paths on Gen8+ as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Kenneth Graunke
2014-06-07 23:52:37 -07:00
parent 45cc9ddcc1
commit 5e6818faa5
2 changed files with 7 additions and 7 deletions
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10
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View File

@@ -421,7 +421,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
case SHADER_OPCODE_TXD:
if (inst->shadow_compare) {
/* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
assert(brw->is_haswell);
assert(brw->gen >= 8 || brw->is_haswell);
msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
@@ -578,7 +578,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
* offset, and each sampler state is only 16-bytes, so we can't
* exclusively use the offset - we have to use both.
*/
assert(brw->is_haswell); /* field only exists on Haswell */
assert(brw->gen >= 8 || brw->is_haswell);
brw_ADD(p,
get_element_ud(header_reg, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
@@ -1384,7 +1384,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_MAD:
assert(brw->gen >= 6);
brw_set_default_access_mode(p, BRW_ALIGN_16);
if (dispatch_width == 16 && !brw->is_haswell) {
if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_MAD(p, dst, src[0], src[1], src[2]);
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1399,7 +1399,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_LRP:
assert(brw->gen >= 6);
brw_set_default_access_mode(p, BRW_ALIGN_16);
if (dispatch_width == 16 && !brw->is_haswell) {
if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_LRP(p, dst, src[0], src[1], src[2]);
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1495,7 +1495,7 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_BFE:
assert(brw->gen >= 7);
brw_set_default_access_mode(p, BRW_ALIGN_16);
if (dispatch_width == 16 && !brw->is_haswell) {
if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_BFE(p, dst, src[0], src[1], src[2]);
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);

4
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View File

@@ -248,7 +248,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
case SHADER_OPCODE_TXD:
if (inst->shadow_compare) {
/* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
assert(brw->is_haswell);
assert(brw->gen >= 8 || brw->is_haswell);
msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
@@ -355,7 +355,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
* offset, and each sampler state is only 16-bytes, so we can't
* exclusively use the offset - we have to use both.
*/
assert(brw->is_haswell); /* field only exists on Haswell */
assert(brw->gen >= 8 || brw->is_haswell);
brw_ADD(p,
get_element_ud(header, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),