anv: Implement VK_KHR_depth_stencil_resolve
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@@ -1130,6 +1130,34 @@ void anv_GetPhysicalDeviceProperties2(
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vk_foreach_struct(ext, pProperties->pNext) {
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switch (ext->sType) {
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
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VkPhysicalDeviceDepthStencilResolvePropertiesKHR *props =
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(VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
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/* We support all of the depth resolve modes */
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props->supportedDepthResolveModes =
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VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
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VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
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VK_RESOLVE_MODE_MIN_BIT_KHR |
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VK_RESOLVE_MODE_MAX_BIT_KHR;
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/* Average doesn't make sense for stencil so we don't support that */
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props->supportedStencilResolveModes =
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VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR;
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if (pdevice->info.gen >= 8) {
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/* The advanced stencil resolve modes currently require stencil
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* sampling be supported by the hardware.
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*/
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props->supportedStencilResolveModes |=
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VK_RESOLVE_MODE_MIN_BIT_KHR |
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VK_RESOLVE_MODE_MAX_BIT_KHR;
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}
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props->independentResolveNone = VK_TRUE;
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props->independentResolve = VK_TRUE;
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
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VkPhysicalDeviceDriverPropertiesKHR *driver_props =
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(VkPhysicalDeviceDriverPropertiesKHR *) ext;
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@@ -76,6 +76,7 @@ EXTENSIONS = [
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Extension('VK_KHR_bind_memory2', 1, True),
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Extension('VK_KHR_create_renderpass2', 1, True),
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Extension('VK_KHR_dedicated_allocation', 1, True),
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Extension('VK_KHR_depth_stencil_resolve', 1, True),
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Extension('VK_KHR_descriptor_update_template', 1, True),
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Extension('VK_KHR_device_group', 1, True),
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Extension('VK_KHR_device_group_creation', 1, True),
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@@ -74,6 +74,10 @@ anv_render_pass_compile(struct anv_render_pass *pass)
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subpass->depth_stencil_attachment->attachment == VK_ATTACHMENT_UNUSED)
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subpass->depth_stencil_attachment = NULL;
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if (subpass->ds_resolve_attachment &&
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subpass->ds_resolve_attachment->attachment == VK_ATTACHMENT_UNUSED)
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subpass->ds_resolve_attachment = NULL;
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for (uint32_t j = 0; j < subpass->attachment_count; j++) {
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struct anv_subpass_attachment *subpass_att = &subpass->attachments[j];
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if (subpass_att->attachment == VK_ATTACHMENT_UNUSED)
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@@ -116,6 +120,16 @@ anv_render_pass_compile(struct anv_render_pass *pass)
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color_att->usage |= VK_IMAGE_USAGE_TRANSFER_SRC_BIT;
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}
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}
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if (subpass->ds_resolve_attachment) {
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struct anv_subpass_attachment *ds_att =
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subpass->depth_stencil_attachment;
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UNUSED struct anv_subpass_attachment *resolve_att =
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subpass->ds_resolve_attachment;
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assert(resolve_att->usage == VK_IMAGE_USAGE_TRANSFER_DST_BIT);
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ds_att->usage |= VK_IMAGE_USAGE_TRANSFER_SRC_BIT;
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}
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}
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/* From the Vulkan 1.0.39 spec:
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@@ -342,10 +356,15 @@ VkResult anv_CreateRenderPass(
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static unsigned
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num_subpass_attachments2(const VkSubpassDescription2KHR *desc)
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{
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const VkSubpassDescriptionDepthStencilResolveKHR *ds_resolve =
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vk_find_struct_const(desc->pNext,
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SUBPASS_DESCRIPTION_DEPTH_STENCIL_RESOLVE_KHR);
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return desc->inputAttachmentCount +
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desc->colorAttachmentCount +
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(desc->pResolveAttachments ? desc->colorAttachmentCount : 0) +
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(desc->pDepthStencilAttachment != NULL);
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(desc->pDepthStencilAttachment != NULL) +
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(ds_resolve && ds_resolve->pDepthStencilResolveAttachment);
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}
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VkResult anv_CreateRenderPass2KHR(
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@@ -460,6 +479,22 @@ VkResult anv_CreateRenderPass2KHR(
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.layout = desc->pDepthStencilAttachment->layout,
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};
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}
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const VkSubpassDescriptionDepthStencilResolveKHR *ds_resolve =
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vk_find_struct_const(desc->pNext,
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SUBPASS_DESCRIPTION_DEPTH_STENCIL_RESOLVE_KHR);
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if (ds_resolve && ds_resolve->pDepthStencilResolveAttachment) {
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subpass->ds_resolve_attachment = subpass_attachments++;
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*subpass->ds_resolve_attachment = (struct anv_subpass_attachment) {
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.usage = VK_IMAGE_USAGE_TRANSFER_DST_BIT,
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.attachment = ds_resolve->pDepthStencilResolveAttachment->attachment,
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.layout = ds_resolve->pDepthStencilResolveAttachment->layout,
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};
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subpass->depth_resolve_mode = ds_resolve->depthResolveMode;
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subpass->stencil_resolve_mode = ds_resolve->stencilResolveMode;
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}
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}
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for (uint32_t i = 0; i < pCreateInfo->dependencyCount; i++)
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@@ -3235,6 +3235,9 @@ struct anv_subpass {
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struct anv_subpass_attachment * resolve_attachments;
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struct anv_subpass_attachment * depth_stencil_attachment;
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struct anv_subpass_attachment * ds_resolve_attachment;
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VkResolveModeFlagBitsKHR depth_resolve_mode;
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VkResolveModeFlagBitsKHR stencil_resolve_mode;
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uint32_t view_mask;
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@@ -3886,6 +3886,23 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
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cmd_buffer_emit_depth_stencil(cmd_buffer);
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}
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static enum blorp_filter
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vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode)
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{
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switch (vk_mode) {
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case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
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return BLORP_FILTER_SAMPLE_0;
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case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
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return BLORP_FILTER_AVERAGE;
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case VK_RESOLVE_MODE_MIN_BIT_KHR:
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return BLORP_FILTER_MIN_SAMPLE;
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case VK_RESOLVE_MODE_MAX_BIT_KHR:
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return BLORP_FILTER_MAX_SAMPLE;
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default:
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return BLORP_FILTER_NONE;
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}
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}
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static void
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cmd_buffer_end_subpass(struct anv_cmd_buffer *cmd_buffer)
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{
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@@ -3953,6 +3970,125 @@ cmd_buffer_end_subpass(struct anv_cmd_buffer *cmd_buffer)
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}
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}
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if (subpass->ds_resolve_attachment) {
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/* We are about to do some MSAA resolves. We need to flush so that the
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* result of writes to the MSAA depth attachments show up in the sampler
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* when we blit to the single-sampled resolve target.
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*/
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cmd_buffer->state.pending_pipe_bits |=
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ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
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uint32_t src_att = subpass->depth_stencil_attachment->attachment;
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uint32_t dst_att = subpass->ds_resolve_attachment->attachment;
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assert(src_att < cmd_buffer->state.pass->attachment_count);
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assert(dst_att < cmd_buffer->state.pass->attachment_count);
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if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
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/* From the Vulkan 1.0 spec:
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*
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* If the first use of an attachment in a render pass is as a
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* resolve attachment, then the loadOp is effectively ignored
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* as the resolve is guaranteed to overwrite all pixels in the
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* render area.
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*/
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cmd_buffer->state.attachments[dst_att].pending_clear_aspects = 0;
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}
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struct anv_image_view *src_iview = fb->attachments[src_att];
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struct anv_image_view *dst_iview = fb->attachments[dst_att];
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const VkRect2D render_area = cmd_buffer->state.render_area;
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if ((src_iview->image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
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subpass->depth_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
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struct anv_attachment_state *src_state =
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&cmd_state->attachments[src_att];
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struct anv_attachment_state *dst_state =
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&cmd_state->attachments[dst_att];
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/* MSAA resolves sample from the source attachment. Transition the
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* depth attachment first to get rid of any HiZ that we may not be
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* able to handle.
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*/
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transition_depth_buffer(cmd_buffer, src_iview->image,
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src_state->current_layout,
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VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
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src_state->aux_usage =
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anv_layout_to_aux_usage(&cmd_buffer->device->info, src_iview->image,
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VK_IMAGE_ASPECT_DEPTH_BIT,
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VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
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src_state->current_layout = VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL;
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/* MSAA resolves write to the resolve attachment as if it were any
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* other transfer op. Transition the resolve attachment accordingly.
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*/
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VkImageLayout dst_initial_layout = dst_state->current_layout;
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/* If our render area is the entire size of the image, we're going to
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* blow it all away so we can claim the initial layout is UNDEFINED
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* and we'll get a HiZ ambiguate instead of a resolve.
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*/
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if (dst_iview->image->type != VK_IMAGE_TYPE_3D &&
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render_area.offset.x == 0 && render_area.offset.y == 0 &&
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render_area.extent.width == dst_iview->extent.width &&
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render_area.extent.height == dst_iview->extent.height)
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dst_initial_layout = VK_IMAGE_LAYOUT_UNDEFINED;
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transition_depth_buffer(cmd_buffer, dst_iview->image,
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dst_initial_layout,
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VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
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dst_state->aux_usage =
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anv_layout_to_aux_usage(&cmd_buffer->device->info, dst_iview->image,
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VK_IMAGE_ASPECT_DEPTH_BIT,
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VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
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dst_state->current_layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL;
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enum blorp_filter filter =
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vk_to_blorp_resolve_mode(subpass->depth_resolve_mode);
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anv_image_msaa_resolve(cmd_buffer,
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src_iview->image, src_state->aux_usage,
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src_iview->planes[0].isl.base_level,
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src_iview->planes[0].isl.base_array_layer,
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dst_iview->image, dst_state->aux_usage,
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dst_iview->planes[0].isl.base_level,
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dst_iview->planes[0].isl.base_array_layer,
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VK_IMAGE_ASPECT_DEPTH_BIT,
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render_area.offset.x, render_area.offset.y,
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render_area.offset.x, render_area.offset.y,
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render_area.extent.width,
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render_area.extent.height,
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fb->layers, filter);
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}
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if ((src_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
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subpass->stencil_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
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enum isl_aux_usage src_aux_usage = ISL_AUX_USAGE_NONE;
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enum isl_aux_usage dst_aux_usage = ISL_AUX_USAGE_NONE;
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enum blorp_filter filter =
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vk_to_blorp_resolve_mode(subpass->stencil_resolve_mode);
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anv_image_msaa_resolve(cmd_buffer,
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src_iview->image, src_aux_usage,
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src_iview->planes[0].isl.base_level,
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src_iview->planes[0].isl.base_array_layer,
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dst_iview->image, dst_aux_usage,
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dst_iview->planes[0].isl.base_level,
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dst_iview->planes[0].isl.base_array_layer,
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VK_IMAGE_ASPECT_STENCIL_BIT,
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render_area.offset.x, render_area.offset.y,
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render_area.offset.x, render_area.offset.y,
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render_area.extent.width,
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render_area.extent.height,
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fb->layers, filter);
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}
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}
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for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
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const uint32_t a = subpass->attachments[i].attachment;
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if (a == VK_ATTACHMENT_UNUSED)
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