From 5df97c27dc8cafbeb27a4ca084e83328a4d1a276 Mon Sep 17 00:00:00 2001
From: Jordan Justen <jordan.l.justen@intel.com>
Date: Mon, 6 Mar 2023 20:14:53 -0800
Subject: [PATCH] intel/compiler: Use nir SUBGROUP_INVOCATION for RT
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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21774>
---
 src/intel/compiler/brw_fs_nir.cpp | 15 ++++-----------
 1 file changed, 4 insertions(+), 11 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 98e55c0c16d..58a1c71893a 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -6189,17 +6189,10 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
             bld.OR(dst, dst, raw_id);
          }
 
-         /* LaneID[0:3] << 0 (We build up LaneID by putting the right number
-          *                   in each lane)
-          */
-         fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UW);
-         const fs_builder ubld8 = bld.exec_all().group(8, 0);
-         ubld8.MOV(quarter(tmp, 0), brw_imm_v(0x76543210));
-         if (bld.dispatch_width() == 16) {
-            /* Sets 0xfedcba98 to the upper part of the register. */
-            ubld8.ADD(quarter(tmp, 1), quarter(tmp, 0), brw_imm_ud(8));
-         }
-         bld.ADD(dst, dst, tmp);
+         /* LaneID[0:3] << 0 (Use nir SYSTEM_VALUE_SUBGROUP_INVOCATION) */
+         assert(bld.dispatch_width() <= 16); /* Limit to 4 bits */
+         bld.ADD(dst, dst,
+                 nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]);
          break;
       }
       default: