OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

a5xx: fix clip_halfz support

Browse Source 
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Ilia Mirkin
2017-07-04 16:02:55 -04:00
parent 02379b68f6
commit 5d9d1df183
3 changed files with 7 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/gallium/drivers/freedreno/a5xx/a5xx.xml.h
View File

@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/ilia/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 141249 bytes, from 2017-07-04 04:13:12)
- /home/ilia/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 141292 bytes, from 2017-07-04 16:29:34)
- /home/ilia/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-11 01:04:14)
- /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-07-04 02:59:47)
- /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-07-04 02:59:47)
@@ -2623,6 +2623,7 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
#define REG_A5XX_UNKNOWN_E001 0x0000e001

3
src/gallium/drivers/freedreno/a5xx/fd5_emit.c
View File

@@ -603,6 +603,9 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
OUT_RING(ring, rasterizer->pc_primitive_cntl |
A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc));
OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
}
if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER)) {

5
src/gallium/drivers/freedreno/a5xx/fd5_rasterizer.c
View File

@@ -55,7 +55,6 @@ fd5_rasterizer_state_create(struct pipe_context *pctx,
psize_max = cso->point_size;
}
so->gras_cl_clip_cntl = 0x80000; /* ??? */
so->gras_su_point_minmax =
A5XX_GRAS_SU_POINT_MINMAX_MIN(psize_min) |
A5XX_GRAS_SU_POINT_MINMAX_MAX(psize_max);
@@ -92,8 +91,8 @@ fd5_rasterizer_state_create(struct pipe_context *pctx,
// if (!cso->depth_clip)
// so->gras_cl_clip_cntl |= A5XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE |
// A5XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE;
// if (cso->clip_halfz)
// so->gras_cl_clip_cntl |= A5XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z;
if (cso->clip_halfz)
so->gras_cl_clip_cntl |= A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z;
return so;
}