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intel/disasm: Disassemble immediate value properly for dim

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On haswell, for dim instruction we encode immediate float value operand
into double float,

v2: Fix comment (Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Sagar Ghuge
2019-03-29 14:04:03 -07:00
committed by Matt Turner
parent 6c83a68ebc
commit 5d7a9e0811
1 changed files with 12 additions and 3 deletions
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15
src/intel/compiler/brw_disasm.c
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@@ -1339,9 +1339,18 @@ imm(FILE *file, const struct gen_device_info *devinfo, enum brw_reg_type type,
format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst)); format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst));
break; break;
case BRW_REGISTER_TYPE_F: case BRW_REGISTER_TYPE_F:
format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96)); /* The DIM instruction's src0 uses an F type but contains a
pad(file, 48); * 64-bit immediate
format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst)); */
if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM) {
format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 64));
pad(file, 48);
format(file, "/* %-gF */", brw_inst_imm_df(devinfo, inst));
} else {
format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96));
pad(file, 48);
format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst));
}
break; break;
case BRW_REGISTER_TYPE_DF: case BRW_REGISTER_TYPE_DF:
format(file, "0x%016"PRIx64"DF", brw_inst_bits(inst, 127, 64)); format(file, "0x%016"PRIx64"DF", brw_inst_bits(inst, 127, 64));