intel/nir/rt: wire position fetch intrinsic

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
This commit is contained in:
Lionel Landwerlin
2022-12-02 13:05:34 +02:00
committed by Marge Bot
parent 03f0f70adf
commit 5cdcc22736
3 changed files with 29 additions and 0 deletions

View File

@@ -471,6 +471,13 @@ lower_ray_query_intrinsic(nir_builder *b,
sysval = world_ray_in.orig;
break;
case nir_ray_query_value_intersection_triangle_vertex_positions: {
struct brw_nir_rt_bvh_primitive_leaf_positions_defs pos;
brw_nir_rt_load_bvh_primitive_leaf_positions(b, &pos, hit_in.prim_leaf_ptr);
sysval = pos.positions[nir_intrinsic_column(intrin)];
break;
}
default:
unreachable("Invalid ray query");
}

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@@ -314,6 +314,13 @@ lower_rt_intrinsics_impl(nir_function_impl *impl,
sysval = build_leaf_is_procedural(b, &hit_in);
break;
case nir_intrinsic_load_ray_triangle_vertex_positions: {
struct brw_nir_rt_bvh_primitive_leaf_positions_defs pos;
brw_nir_rt_load_bvh_primitive_leaf_positions(b, &pos, hit_in.prim_leaf_ptr);
sysval = pos.positions[nir_intrinsic_column(intrin)];
break;
}
case nir_intrinsic_load_leaf_opaque_intel: {
if (stage == MESA_SHADER_INTERSECTION) {
/* In intersection shaders, the opaque bit is passed to us in

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@@ -904,6 +904,21 @@ brw_nir_rt_load_bvh_primitive_leaf(nir_builder *b,
nir_imm_int(b, 31), nir_imm_int(b, 30));
}
struct brw_nir_rt_bvh_primitive_leaf_positions_defs {
nir_ssa_def *positions[3];
};
static inline void
brw_nir_rt_load_bvh_primitive_leaf_positions(nir_builder *b,
struct brw_nir_rt_bvh_primitive_leaf_positions_defs *defs,
nir_ssa_def *leaf_addr)
{
for (unsigned i = 0; i < ARRAY_SIZE(defs->positions); i++) {
defs->positions[i] =
brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 16 + i * 4 * 3), 4, 3, 32);
}
}
static inline nir_ssa_def *
brw_nir_rt_load_primitive_id_from_hit(nir_builder *b,
nir_ssa_def *is_procedural,