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agx: Pass mask into ld/st_tile instructions

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Properly handle render target formats with <4 components.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18687>
This commit is contained in:
Alyssa Rosenzweig
2022-09-11 12:02:32 -04:00
committed by Marge Bot
parent 640fd089a2
commit 5cd2371318
3 changed files with 10 additions and 9 deletions
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9
src/asahi/compiler/agx_compile.c
View File

@@ -475,7 +475,8 @@ agx_emit_fragment_out(agx_builder *b, nir_intrinsic_instr *instr)
b->shader->did_writeout = true;
return agx_st_tile(b, agx_src_index(&instr->src[0]),
b->shader->key->fs.tib_formats[rt]);
b->shader->key->fs.tib_formats[rt],
nir_intrinsic_write_mask(instr));
}
static void
@@ -494,8 +495,10 @@ agx_emit_load_tile(agx_builder *b, agx_index dest, nir_intrinsic_instr *instr)
b->shader->did_writeout = true;
b->shader->out->reads_tib = true;
agx_ld_tile_to(b, dest, b->shader->key->fs.tib_formats[rt]);
agx_emit_cached_split(b, dest, 4);
unsigned nr_comps = nir_dest_num_components(instr->dest);
agx_ld_tile_to(b, dest, b->shader->key->fs.tib_formats[rt],
BITFIELD_MASK(nr_comps));
agx_emit_cached_split(b, dest, nr_comps);
}
static enum agx_format

5
src/asahi/compiler/agx_opcodes.py
View File

@@ -221,11 +221,10 @@ op("get_sr", (0x72, 0x7F | L, 4, _), dests = 1, imms = [SR])
op("sample_mask", (0x7fc1, 0xffff, 6, _), dests = 0, srcs = 1, can_eliminate = False)
# Essentially same encoding
op("ld_tile", (0x49, 0x7F, 8, _), dests = 1, srcs = 0,
can_eliminate = False, imms = [FORMAT])
op("ld_tile", (0x49, 0x7F, 8, _), dests = 1, srcs = 0, imms = [FORMAT, MASK])
op("st_tile", (0x09, 0x7F, 8, _), dests = 0, srcs = 1,
can_eliminate = False, imms = [FORMAT])
can_eliminate = False, imms = [FORMAT, MASK])
for (name, exact) in [("any", 0xC000), ("none", 0xC200)]:
op("jmp_exec_" + name, (exact, (1 << 16) - 1, 6, _), dests = 0, srcs = 0,

5
src/asahi/compiler/agx_pack.c
View File

@@ -426,8 +426,7 @@ agx_pack_instr(struct util_dynarray *emission, struct util_dynarray *fixups, agx
bool load = (I->op == AGX_OPCODE_LD_TILE);
unsigned D = agx_pack_alu_dst(load ? I->dest[0] : I->src[0]);
unsigned rt = 0; /* TODO */
unsigned mask = I->mask ?: 0xF;
assert(mask < 0x10);
assert(I->mask < 0x10);
uint64_t raw =
0x09 |
@@ -436,7 +435,7 @@ agx_pack_instr(struct util_dynarray *emission, struct util_dynarray *fixups, agx
((uint64_t) (I->format) << 24) |
((uint64_t) (rt) << 32) |
(load ? (1ull << 35) : 0) |
((uint64_t) (mask) << 36) |
((uint64_t) (I->mask) << 36) |
((uint64_t) 0x0380FC << 40) |
(((uint64_t) (D >> 8)) << 60);