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radv: simplify load_sample_mask_in lowering

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From the Vulkan spec:
    "Sample shading is enabled if at least one of the following
     conditions is true:

     - VkPipelineMultisampleStateCreateInfo::sampleShadingEnable is
       set to VK_TRUE, or
     - the fragment shader’s entry point interface includes input
       variables decorated with a BuiltIn of SampleId or SamplePosition
       built-ins."

We don't need to pass the number of rasterization samples, checking
for sample shading is enough. This will help for dynamic rasterization
samples.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19654>
This commit is contained in:
Samuel Pitoiset
2022-11-10 17:19:19 +01:00
committed by Marge Bot
parent 0097592f8c
commit 5c9ade2464
3 changed files with 7 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/amd/vulkan/radv_pipeline.c
View File

@@ -2829,10 +2829,11 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin
if (state->ts)
key.tcs.tess_input_vertices = state->ts->patch_control_points;
if (state->ms && state->ms->rasterization_samples > 1) {
uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(state);
if (state->ms) {
key.ps.sample_shading_enable = state->ms->sample_shading_enable;
if (state->ms->rasterization_samples > 1) {
key.ps.num_samples = state->ms->rasterization_samples;
key.ps.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
}
}
key.ps.col_format = blend->spi_shader_col_format;

10
src/amd/vulkan/radv_shader.c
View File

@@ -546,19 +546,11 @@ radv_lower_fs_intrinsics(nir_shader *nir, const struct radv_pipeline_stage *fs_s
switch (intrin->intrinsic) {
case nir_intrinsic_load_sample_mask_in: {
uint8_t log2_ps_iter_samples;
if (info->ps.uses_sample_shading) {
log2_ps_iter_samples = util_logbase2(key->ps.num_samples);
} else {
log2_ps_iter_samples = key->ps.log2_ps_iter_samples;
}
nir_ssa_def *sample_coverage =
nir_load_vector_arg_amd(&b, 1, .base = args->ac.sample_coverage.arg_index);
nir_ssa_def *def = NULL;
if (log2_ps_iter_samples) {
if (info->ps.uses_sample_shading || key->ps.sample_shading_enable) {
/* gl_SampleMaskIn[0] = (SampleCoverage & (1 << gl_SampleID)). */
nir_ssa_def *sample_id = nir_load_sample_id(&b);
def = nir_iand(&b, sample_coverage, nir_ishl(&b, nir_imm_int(&b, 1u), sample_id));

2
src/amd/vulkan/radv_shader.h
View File

@@ -89,8 +89,8 @@ struct radv_pipeline_key {
uint32_t is_int8;
uint32_t is_int10;
uint32_t cb_target_mask;
uint8_t log2_ps_iter_samples;
uint8_t num_samples;
bool sample_shading_enable;
bool mrt0_is_dual_src;
bool lower_discard_to_demote;