agx: Handle 64-bit moves

lower_resinfo generates some 64-bit math, so we need to handle it. Even
though we don't have native 64-bit moves, it's convenient to pretend we
do to avoid special cases in the IR. In particular, modelling 64-bit
mov_imm in the IR means our existing small constant propagation code
works, with zero-extension from 8->64.

Fixes dEQP-GLES3.functional.texture.units.2_units.only_2d_array.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>

src/asahi/compiler/agx_compile.c

@@ -257,7 +257,6 @@ agx_emit_load_const(agx_builder *b, nir_load_const_instr *instr)
    /* Ensure we've been scalarized and bit size lowered */
    unsigned bit_size = instr->def.bit_size;
    assert(instr->def.num_components == 1);
-   assert(bit_size == 1 || bit_size == 16 || bit_size == 32);
 
    /* Emit move, later passes can inline/push if useful */
    agx_mov_imm_to(b,
@@ -1819,6 +1818,7 @@ agx_compile_function_nir(nir_shader *nir, nir_function_impl *impl,
    }
 
    agx_ra(ctx);
+   agx_lower_64bit_postra(ctx);
 
    if (ctx->stage == MESA_SHADER_VERTEX)
       agx_set_st_vary_final(ctx);

src/asahi/compiler/agx_compiler.h

@@ -292,7 +292,7 @@ typedef struct {
    uint8_t nr_srcs;
 
    union {
-      uint32_t imm;
+      uint64_t imm;
       uint32_t writeout;
       uint32_t truth_table;
       uint32_t component;
@@ -755,6 +755,7 @@ void agx_optimizer(agx_context *ctx);
 void agx_lower_pseudo(agx_context *ctx);
 void agx_dce(agx_context *ctx);
 void agx_ra(agx_context *ctx);
+void agx_lower_64bit_postra(agx_context *ctx);
 void agx_pack_binary(agx_context *ctx, struct util_dynarray *emission);
 
 #ifndef NDEBUG

src/asahi/compiler/agx_lower_64bit.c

@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2022 Alyssa Rosenzweig <alyssa@rosenzweig.io>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "agx_compiler.h"
+#include "agx_builder.h"
+
+/*
+ * Lower 64-bit moves to 32-bit moves. Although there are not 64-bit moves in
+ * the ISA, it is convenient to pretend there are for instruction selection.
+ * They are lowered trivially after register allocation.
+ *
+ * General 64-bit lowering happens in nir_lower_int64.
+ */
+static bool
+lower(agx_builder *b, agx_instr *I)
+{
+   if (I->op != AGX_OPCODE_MOV && I->op != AGX_OPCODE_MOV_IMM)
+      return false;
+
+   if (I->dest[0].size != AGX_SIZE_64)
+      return false;
+
+   agx_index dest = I->dest[0];
+   dest.size = AGX_SIZE_32;
+
+   if (I->op == AGX_OPCODE_MOV) {
+      assert(I->src[0].type == AGX_INDEX_REGISTER ||
+             I->src[0].type == AGX_INDEX_UNIFORM);
+      assert(I->src[0].size == AGX_SIZE_64);
+      agx_index src = I->src[0];
+      src.size = AGX_SIZE_32;
+
+      /* Low 32-bit */
+      agx_mov_to(b, dest, src);
+
+      /* High 32-bits */
+      dest.value += 2;
+      src.value += 2;
+      agx_mov_to(b, dest, src);
+   } else {
+      /* Low 32-bit */
+      agx_mov_imm_to(b, dest, I->imm & BITFIELD_MASK(32));
+
+      /* High 32-bits */
+      dest.value += 2;
+      agx_mov_imm_to(b, dest, I->imm >> 32);
+   }
+
+   return true;
+}
+
+void
+agx_lower_64bit_postra(agx_context *ctx)
+{
+   agx_foreach_instr_global_safe(ctx, I) {
+      agx_builder b = agx_init_builder(ctx, agx_before_instr(I));
+
+      if (lower(&b, I))
+         agx_remove_instruction(I);
+   }
+}

src/asahi/compiler/agx_optimizer.c

@@ -187,6 +187,11 @@ agx_optimizer_copyprop(agx_instr **defs, agx_instr *I)
            I->op == AGX_OPCODE_ST_VARY))
           continue;
 
+      /* ALU instructions cannot take 64-bit */
+      if (def->src[0].size == AGX_SIZE_64 &&
+          !(I->op == AGX_OPCODE_DEVICE_LOAD && s == 0))
+         continue;
+
       I->src[s] = agx_replace_index(src, def->src[0]);
    }
 }

src/asahi/compiler/agx_print.c

@@ -164,7 +164,7 @@ agx_print_instr(agx_instr *I, FILE *fp)
       else
          print_comma = true;
 
-      fprintf(fp, "#%X", I->imm);
+      fprintf(fp, "#%" PRIx64, I->imm);
    }
 
    if (info.immediates & AGX_IMMEDIATE_DIM) {

src/asahi/compiler/meson.build

@@ -24,6 +24,7 @@ libasahi_agx_files = files(
   'agx_dce.c',
   'agx_liveness.c',
   'agx_nir_lower_array_texture.c',
+  'agx_lower_64bit.c',
   'agx_lower_resinfo.c',
   'agx_lower_parallel_copy.c',
   'agx_lower_pseudo.c',