radv/gfx10: implement support for GS as NGG

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-11 08:44:16 +02:00
parent 7286865f6d
commit 5bbcb3f5bc
4 changed files with 568 additions and 6 deletions
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -105,7 +105,12 @@ struct radv_shader_context {

 	bool is_gs_copy_shader;
 	LLVMValueRef gs_next_vertex[4];
+	LLVMValueRef gs_curprim_verts[4];
+	LLVMValueRef gs_generated_prims[4];
+	LLVMValueRef gs_ngg_emit;
+	LLVMValueRef gs_ngg_scratch;
 	unsigned gs_max_out_vertices;
+	unsigned gs_output_prim;

 	unsigned tes_primitive_mode;

@@ -116,6 +121,8 @@ struct radv_shader_context {
 	uint32_t tcs_num_patches;
 	uint32_t max_gsvs_emit_size;
 	uint32_t gsvs_vertex_size;
+
+	LLVMValueRef vertexptr; /* GFX10 only */
 };

 enum radeon_llvm_calling_convention {
@@ -1846,6 +1853,10 @@ static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
 }


+static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
+				     unsigned stream,
+				     LLVMValueRef *addrs);
+
 static void
 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
 {
@@ -1854,6 +1865,11 @@ visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addr
 	unsigned offset = 0;
 	struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);

+	if (ctx->options->key.vs_common_out.as_ngg) {
+		gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
+		return;
+	}
+
 	/* Write vertex attribute values to GSVS ring */
 	gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
 				       ctx->gs_next_vertex[stream],
@@ -1919,6 +1935,12 @@ static void
 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
 {
 	struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
+
+	if (ctx->options->key.vs_common_out.as_ngg) {
+		LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
+		return;
+	}
+
 	ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
 }

@@ -2571,8 +2593,20 @@ radv_export_param(struct radv_shader_context *ctx, unsigned index,
 static LLVMValueRef
 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
 {
-	LLVMValueRef output =
-		ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
+	LLVMValueRef output;
+
+	if (ctx->vertexptr) {
+		LLVMValueRef gep_idx[3] = {
+			ctx->ac.i32_0, /* implicit C-style array */
+			ctx->ac.i32_0, /* second value of struct */
+			ctx->ac.i32_1, /* stream 1: source data index */
+		};
+
+		gep_idx[2] = LLVMConstInt(ctx->ac.i32, ac_llvm_reg_index_soa(index, chan), false);
+		output = LLVMBuildGEP(ctx->ac.builder, ctx->vertexptr, gep_idx, 3, "");
+	} else {
+		output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
+	}

 	return LLVMBuildLoad(ctx->ac.builder, output, "");
 }
@@ -2940,7 +2974,7 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
 			outputs[noutput].usage_mask =
 				ctx->shader_info->info.tes.output_usage_mask[i];
 		} else {
-			assert(ctx->is_gs_copy_shader);
+			assert(ctx->is_gs_copy_shader || ctx->options->key.vs_common_out.as_ngg);
 			outputs[noutput].usage_mask =
 				ctx->shader_info->info.gs.output_usage_mask[i];
 		}
@@ -3090,6 +3124,20 @@ static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
 	return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
 }

+static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
+{
+	return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 28, 4);
+}
+
+static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
+{
+	LLVMBuilderRef builder = ctx->ac.builder;
+	LLVMValueRef tmp;
+	tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
+			   LLVMConstInt(ctx->ac.i32, 64, false), "");
+	return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
+}
+
 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
 {
 	return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
@@ -3106,6 +3154,85 @@ static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
 			    false);
 }

+static LLVMValueRef
+ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
+{
+	unsigned num_outputs = util_bitcount64(ctx->output_mask);
+
+	LLVMTypeRef elements[2] = {
+		LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
+		LLVMArrayType(ctx->ac.i8, 4),
+	};
+	LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
+	type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
+	return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
+}
+
+/**
+ * Return a pointer to the LDS storage reserved for the N'th vertex, where N
+ * is in emit order; that is:
+ * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
+ * - during vertex emit, i.e. while the API GS shader invocation is running,
+ *   N = threadidx * gs_max_out_vertices + emitidx
+ *
+ * Goals of the LDS memory layout:
+ * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
+ *    in uniform control flow
+ * 2. Eliminate bank conflicts on read for export if, additionally, there is no
+ *    culling
+ * 3. Agnostic to the number of waves (since we don't know it before compiling)
+ * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
+ * 5. Avoid wasting memory.
+ *
+ * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
+ * layout, elimination of bank conflicts requires that each vertex occupy an
+ * odd number of dwords. We use the additional dword to store the output stream
+ * index as well as a flag to indicate whether this vertex ends a primitive
+ * for rasterization.
+ *
+ * Swizzling is required to satisfy points 1 and 2 simultaneously.
+ *
+ * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
+ * Indices are swizzled in groups of 32, which ensures point 1 without
+ * disturbing point 2.
+ *
+ * \return an LDS pointer to type {[N x i32], [4 x i8]}
+ */
+static LLVMValueRef
+ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
+{
+	LLVMBuilderRef builder = ctx->ac.builder;
+	LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
+
+	/* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
+	unsigned write_stride_2exp = ffs(ctx->gs_max_out_vertices) - 1;
+	if (write_stride_2exp) {
+		LLVMValueRef row =
+			LLVMBuildLShr(builder, vertexidx,
+				      LLVMConstInt(ctx->ac.i32, 5, false), "");
+		LLVMValueRef swizzle =
+			LLVMBuildAnd(builder, row,
+				     LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
+						  false), "");
+		vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
+	}
+
+	return ac_build_gep0(&ctx->ac, storage, vertexidx);
+}
+
+static LLVMValueRef
+ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
+		       LLVMValueRef emitidx)
+{
+	LLVMBuilderRef builder = ctx->ac.builder;
+	LLVMValueRef tmp;
+
+	tmp = LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false);
+	tmp = LLVMBuildMul(builder, tmp, gsthread, "");
+	const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
+	return ngg_gs_vertex_ptr(ctx, vertexidx);
+}
+
 /* Send GS Alloc Req message from the first wave of the group to SPI.
 * Message payload is:
 * - bits 0..10: vertices in group
@@ -3247,6 +3374,369 @@ handle_ngg_outputs_post(struct radv_shader_context *ctx)
 	ac_nir_build_endif(&if_state);
 }

+static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
+{
+	/* Zero out the part of LDS scratch that is used to accumulate the
+	 * per-stream generated primitive count.
+	 */
+	LLVMBuilderRef builder = ctx->ac.builder;
+	LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
+	LLVMValueRef tid = get_thread_id_in_tg(ctx);
+	LLVMValueRef tmp;
+
+	tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
+	ac_build_ifcc(&ctx->ac, tmp, 5090);
+	{
+		LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
+		LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
+	}
+	ac_build_endif(&ctx->ac, 5090);
+
+	ac_build_s_barrier(&ctx->ac);
+}
+
+static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
+{
+	LLVMBuilderRef builder = ctx->ac.builder;
+	LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
+	LLVMValueRef tmp;
+
+	/* Zero out remaining (non-emitted) primitive flags.
+	 *
+	 * Note: Alternatively, we could pass the relevant gs_next_vertex to
+	 *       the emit threads via LDS. This is likely worse in the expected
+	 *       typical case where each GS thread emits the full set of
+	 *       vertices.
+	 */
+	for (unsigned stream = 0; stream < 4; ++stream) {
+		unsigned num_components;
+
+		num_components =
+			ctx->shader_info->info.gs.num_stream_output_components[stream];
+		if (!num_components)
+			continue;
+
+		const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
+
+		ac_build_bgnloop(&ctx->ac, 5100);
+
+		const LLVMValueRef vertexidx =
+			LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
+		tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
+			LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
+		ac_build_ifcc(&ctx->ac, tmp, 5101);
+		ac_build_break(&ctx->ac);
+		ac_build_endif(&ctx->ac, 5101);
+
+		tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
+		LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
+
+		tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
+		LLVMValueRef gep_idx[3] = {
+			ctx->ac.i32_0, /* implied C-style array */
+			ctx->ac.i32_1, /* second entry of struct */
+			LLVMConstInt(ctx->ac.i32, stream, false),
+		};
+		tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
+		LLVMBuildStore(builder, i8_0, tmp);
+
+		ac_build_endloop(&ctx->ac, 5100);
+	}
+}
+
+static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
+{
+	const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->gs_output_prim);
+	LLVMBuilderRef builder = ctx->ac.builder;
+	LLVMValueRef tmp, tmp2;
+
+	ac_build_s_barrier(&ctx->ac);
+
+	const LLVMValueRef tid = get_thread_id_in_tg(ctx);
+	LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
+
+	/* TODO: streamout */
+
+	/* TODO: culling */
+
+	/* Determine vertex liveness. */
+	LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
+
+	tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
+	ac_build_ifcc(&ctx->ac, tmp, 5120);
+	{
+		for (unsigned i = 0; i < verts_per_prim; ++i) {
+			const LLVMValueRef primidx =
+				LLVMBuildAdd(builder, tid,
+					     LLVMConstInt(ctx->ac.i32, i, false), "");
+
+			if (i > 0) {
+				tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
+				ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
+			}
+
+			/* Load primitive liveness */
+			tmp = ngg_gs_vertex_ptr(ctx, primidx);
+			LLVMValueRef gep_idx[3] = {
+				ctx->ac.i32_0, /* implicit C-style array */
+				ctx->ac.i32_1, /* second value of struct */
+				ctx->ac.i32_0, /* stream 0 */
+			};
+			tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
+			tmp = LLVMBuildLoad(builder, tmp, "");
+			const LLVMValueRef primlive =
+				LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
+
+			tmp = LLVMBuildLoad(builder, vertliveptr, "");
+			tmp = LLVMBuildOr(builder, tmp, primlive, ""),
+			LLVMBuildStore(builder, tmp, vertliveptr);
+
+			if (i > 0)
+				ac_build_endif(&ctx->ac, 5121 + i);
+		}
+	}
+	ac_build_endif(&ctx->ac, 5120);
+
+	/* Inclusive scan addition across the current wave. */
+	LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
+	struct ac_wg_scan vertlive_scan = {};
+	vertlive_scan.op = nir_op_iadd;
+	vertlive_scan.enable_reduce = true;
+	vertlive_scan.enable_exclusive = true;
+	vertlive_scan.src = vertlive;
+	vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
+	vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
+	vertlive_scan.numwaves = get_tgsize(ctx);
+	vertlive_scan.maxwaves = 8;
+
+	ac_build_wg_scan(&ctx->ac, &vertlive_scan);
+
+	/* Skip all exports (including index exports) when possible. At least on
+	 * early gfx10 revisions this is also to avoid hangs.
+	 */
+	LLVMValueRef have_exports =
+		LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
+	num_emit_threads =
+		LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
+
+	/* Allocate export space. Send this message as early as possible, to
+	 * hide the latency of the SQ <-> SPI roundtrip.
+	 *
+	 * Note: We could consider compacting primitives for export as well.
+	 *       PA processes 1 non-null prim / clock, but it fetches 4 DW of
+	 *       prim data per clock and skips null primitives at no additional
+	 *       cost. So compacting primitives can only be beneficial when
+	 *       there are 4 or more contiguous null primitives in the export
+	 *       (in the common case of single-dword prim exports).
+	 */
+	build_sendmsg_gs_alloc_req(ctx, vertlive_scan.result_reduce, num_emit_threads);
+
+	/* Setup the reverse vertex compaction permutation. We re-use stream 1
+	 * of the primitive liveness flags, relying on the fact that each
+	 * threadgroup can have at most 256 threads. */
+	ac_build_ifcc(&ctx->ac, vertlive, 5130);
+	{
+		tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
+		LLVMValueRef gep_idx[3] = {
+			ctx->ac.i32_0, /* implicit C-style array */
+			ctx->ac.i32_1, /* second value of struct */
+			ctx->ac.i32_1, /* stream 1 */
+		};
+		tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
+		tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
+		LLVMBuildStore(builder, tmp2, tmp);
+	}
+	ac_build_endif(&ctx->ac, 5130);
+
+	ac_build_s_barrier(&ctx->ac);
+
+	/* Export primitive data */
+	tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
+	ac_build_ifcc(&ctx->ac, tmp, 5140);
+	{
+		struct ngg_prim prim = {};
+		prim.num_vertices = verts_per_prim;
+
+		tmp = ngg_gs_vertex_ptr(ctx, tid);
+		LLVMValueRef gep_idx[3] = {
+			ctx->ac.i32_0, /* implicit C-style array */
+			ctx->ac.i32_1, /* second value of struct */
+			ctx->ac.i32_0, /* primflag */
+		};
+		tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
+		tmp = LLVMBuildLoad(builder, tmp, "");
+		prim.isnull = LLVMBuildICmp(builder, LLVMIntEQ, tmp,
+					    LLVMConstInt(ctx->ac.i8, 0, false), "");
+
+		for (unsigned i = 0; i < verts_per_prim; ++i) {
+			prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
+				LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
+			prim.edgeflag[i] = ctx->ac.i1false;
+		}
+
+		build_export_prim(ctx, &prim);
+	}
+	ac_build_endif(&ctx->ac, 5140);
+
+	/* Export position and parameter data */
+	tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
+	ac_build_ifcc(&ctx->ac, tmp, 5145);
+	{
+		struct radv_vs_output_info *outinfo = &ctx->shader_info->vs.outinfo;
+		struct radv_shader_output_values *outputs;
+		unsigned noutput = 0;
+
+		/* Allocate a temporary array for the output values. */
+		unsigned num_outputs = util_bitcount64(ctx->output_mask);
+		outputs = calloc(num_outputs, sizeof(outputs[0]));
+
+		memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
+		       sizeof(outinfo->vs_output_param_offset));
+		outinfo->pos_exports = 0;
+
+		tmp = ngg_gs_vertex_ptr(ctx, tid);
+		LLVMValueRef gep_idx[3] = {
+			ctx->ac.i32_0, /* implicit C-style array */
+			ctx->ac.i32_1, /* second value of struct */
+			ctx->ac.i32_1, /* stream 1: source data index */
+		};
+		tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
+		tmp = LLVMBuildLoad(builder, tmp, "");
+		tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
+		const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
+
+		if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
+			outinfo->writes_pointsize = true;
+		}
+
+		if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
+			outinfo->writes_layer = true;
+		}
+
+		if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
+			outinfo->writes_viewport_index = true;
+		}
+
+		unsigned out_idx = 0;
+		gep_idx[1] = ctx->ac.i32_0;
+		for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+			if (!(ctx->output_mask & (1ull << i)))
+				continue;
+
+			outputs[noutput].slot_name = i;
+			outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
+
+			if (ctx->stage == MESA_SHADER_VERTEX &&
+			    !ctx->is_gs_copy_shader) {
+				outputs[noutput].usage_mask =
+					ctx->shader_info->info.vs.output_usage_mask[i];
+			} else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
+				outputs[noutput].usage_mask =
+					ctx->shader_info->info.tes.output_usage_mask[i];
+			} else {
+				assert(ctx->is_gs_copy_shader || ctx->options->key.vs_common_out.as_ngg);
+				outputs[noutput].usage_mask =
+					ctx->shader_info->info.gs.output_usage_mask[i];
+			}
+
+			for (unsigned j = 0; j < 4; j++, out_idx++) {
+				gep_idx[2] = LLVMConstInt(ctx->ac.i32, out_idx, false);
+				tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
+				tmp = LLVMBuildLoad(builder, tmp, "");
+				outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
+			}
+
+			noutput++;
+		}
+
+		radv_llvm_export_vs(ctx, outputs, noutput, outinfo, false);
+		FREE(outputs);
+	}
+	ac_build_endif(&ctx->ac, 5145);
+}
+
+static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
+				     unsigned stream,
+				     LLVMValueRef *addrs)
+{
+	LLVMBuilderRef builder = ctx->ac.builder;
+	LLVMValueRef tmp;
+	const LLVMValueRef vertexidx =
+		LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
+
+	/* If this thread has already emitted the declared maximum number of
+	 * vertices, skip the write: excessive vertex emissions are not
+	 * supposed to have any effect.
+	 */
+	const LLVMValueRef can_emit =
+		LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
+			      LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
+	ac_build_kill_if_false(&ctx->ac, can_emit);
+
+	tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
+	tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
+	LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
+
+	const LLVMValueRef vertexptr =
+		ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
+	unsigned out_idx = 0;
+	for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+		unsigned output_usage_mask =
+			ctx->shader_info->info.gs.output_usage_mask[i];
+		uint8_t output_stream =
+			ctx->shader_info->info.gs.output_streams[i];
+		LLVMValueRef *out_ptr = &addrs[i * 4];
+		int length = util_last_bit(output_usage_mask);
+
+		if (!(ctx->output_mask & (1ull << i)) ||
+		    output_stream != stream)
+			continue;
+
+		for (unsigned j = 0; j < length; j++, out_idx++) {
+			if (!(output_usage_mask & (1 << j)))
+				continue;
+
+			LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
+							     out_ptr[j], "");
+			LLVMValueRef gep_idx[3] = {
+				ctx->ac.i32_0, /* implied C-style array */
+				ctx->ac.i32_0, /* first entry of struct */
+				LLVMConstInt(ctx->ac.i32, out_idx, false),
+			};
+			LLVMValueRef ptr = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
+
+			out_val = ac_to_integer(&ctx->ac, out_val);
+			LLVMBuildStore(builder, out_val, ptr);
+		}
+	}
+	assert(out_idx * 4 <= ctx->gsvs_vertex_size);
+
+	/* Determine and store whether this vertex completed a primitive. */
+	const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
+
+	tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->gs_output_prim) - 1, false);
+	const LLVMValueRef iscompleteprim =
+		LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
+
+	tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
+	LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
+
+	LLVMValueRef gep_idx[3] = {
+		ctx->ac.i32_0, /* implied C-style array */
+		ctx->ac.i32_1, /* second struct entry */
+		LLVMConstInt(ctx->ac.i32, stream, false),
+	};
+	const LLVMValueRef primflagptr =
+		LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
+
+	tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
+	LLVMBuildStore(builder, tmp, primflagptr);
+
+	tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
+	tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
+	LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
+}
+
 static void
 write_tess_factors(struct radv_shader_context *ctx)
 {
@@ -3490,6 +3980,14 @@ handle_fs_outputs_post(struct radv_shader_context *ctx)
 static void
 emit_gs_epilogue(struct radv_shader_context *ctx)
 {
+	if (ctx->options->key.vs_common_out.as_ngg) {
+		gfx10_ngg_gs_emit_epilogue_1(ctx);
+		return;
+	}
+
+	if (ctx->ac.chip_class >= GFX10)
+		LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
+
 	ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
 }

@@ -3503,10 +4001,10 @@ handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
 	case MESA_SHADER_VERTEX:
 		if (ctx->options->key.vs_common_out.as_ls)
 			handle_ls_outputs_post(ctx);
-		else if (ctx->options->key.vs_common_out.as_ngg)
-			break; /* handled outside of the shader body */
 		else if (ctx->options->key.vs_common_out.as_es)
 			handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
+		else if (ctx->options->key.vs_common_out.as_ngg)
+			break; /* handled outside of the shader body */
 		else
 			handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
 					       ctx->options->key.vs_common_out.export_clip_dists,
@@ -3800,7 +4298,31 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
 				ctx.gs_next_vertex[i] =
 					ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
 			}
+			if (ctx.options->key.vs_common_out.as_ngg) {
+				for (unsigned i = 0; i < 4; ++i) {
+					ctx.gs_curprim_verts[i] =
+						ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
+					ctx.gs_generated_prims[i] =
+						ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
+				}
+
+				/* TODO: streamout */
+
+				LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, 8);
+				ctx.gs_ngg_scratch =
+					LLVMAddGlobalInAddressSpace(ctx.ac.module,
+								    ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
+				LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
+				LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
+
+				ctx.gs_ngg_emit = LLVMBuildIntToPtr(ctx.ac.builder, ctx.ac.i32_0,
+					LLVMPointerType(LLVMArrayType(ctx.ac.i32, 0), AC_ADDR_SPACE_LDS),
+					"ngg_emit");
+				LLVMSetAlignment(ctx.gs_ngg_emit, 4);
+			}
+
 			ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
+			ctx.gs_output_prim = shaders[i]->info.gs.output_primitive;
 			ctx.abi.load_inputs = load_gs_input;
 			ctx.abi.emit_primitive = visit_end_primitive;
 		} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
@@ -3861,6 +4383,11 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
 			LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);

 			LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
+
+			if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
+			    ctx.options->key.vs_common_out.as_ngg) {
+				gfx10_ngg_gs_emit_prologue(&ctx);
+			}
 		}

 		if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
@@ -3883,6 +4410,9 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
 		    ctx.options->key.vs_common_out.as_ngg &&
 		    i == shader_count - 1) {
 			handle_ngg_outputs_post(&ctx);
+		} else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
+			   ctx.options->key.vs_common_out.as_ngg) {
+			gfx10_ngg_gs_emit_epilogue_2(&ctx);
 		}

 		if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2023,7 +2023,10 @@ static const struct radv_prim_vertex_count prim_size_table[] = {
 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
 {
 	if (radv_pipeline_has_gs(pipeline))
-		return &pipeline->gs_copy_shader->info.vs.outinfo;
+		if (radv_pipeline_has_ngg(pipeline))
+			return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
+		else
+			return &pipeline->gs_copy_shader->info.vs.outinfo;
 	else if (radv_pipeline_has_tess(pipeline))
 		return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
 	else
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -2148,6 +2148,30 @@ struct radeon_winsys_sem;

 uint64_t radv_get_current_time(void);

+static inline uint32_t
+si_conv_gl_prim_to_vertices(unsigned gl_prim)
+{
+	switch (gl_prim) {
+	case 0: /* GL_POINTS */
+		return 1;
+	case 1: /* GL_LINES */
+	case 3: /* GL_LINE_STRIP */
+		return 2;
+	case 4: /* GL_TRIANGLES */
+	case 5: /* GL_TRIANGLE_STRIP */
+		return 3;
+	case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
+		return 4;
+	case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
+		return 6;
+	case 7: /* GL_QUADS */
+		return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
+	default:
+		assert(0);
+		return 0;
+	}
+}
+
 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)		\
 								\
 	static inline struct __radv_type *			\
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -927,6 +927,11 @@ radv_shader_variant_create(struct radv_device *device,
 			sym->name = "esgs_ring";
 			sym->size = 32 * 1024;
 			sym->align = 64 * 1024;
+
+			/* Make sure to have LDS space for NGG scratch. */
+			/* TODO: Compute this correctly somehow? */
+			if (binary->variant_info.is_ngg)
+				sym->size -= 32;
 		}
 		struct ac_rtld_open_info open_info = {
 			.info = &device->physical_device->rad_info,