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radeonsi/gfx11: ignore alpha_is_on_msb because the hw ignores it

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
This commit is contained in:
Marek Olšák
2023-02-18 02:33:32 -05:00
committed by Marge Bot
parent 52f5b7a970
commit 5b85fa6031
2 changed files with 32 additions and 31 deletions
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59
src/gallium/drivers/radeonsi/si_clear.c
View File

@@ -169,6 +169,9 @@ enum pipe_format si_simplify_cb_format(enum pipe_format format)
bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format)
{
if (sscreen->info.gfx_level >= GFX11)
return false;
format = si_simplify_cb_format(format);
const struct util_format_description *desc = util_format_description(format);
unsigned comp_swap = si_translate_colorswap(sscreen->info.gfx_level, format, false);
@@ -382,35 +385,33 @@ static bool gfx11_get_dcc_clear_parameters(struct si_screen *sscreen, enum pipe_
}
/* Check 0001 and 1110 cases. */
if (vi_alpha_is_on_msb(sscreen, surface_format)) {
if (desc->nr_channels == 2 && desc->channel[0].size == 8) {
if (value.ub[0] == 0x00 && value.ub[1] == 0xff) {
*clear_value = GFX11_DCC_CLEAR_0001_UNORM;
return true;
} else if (value.ub[0] == 0xff && value.ub[1] == 0x00) {
*clear_value = GFX11_DCC_CLEAR_1110_UNORM;
return true;
}
} else if (desc->nr_channels == 4 && desc->channel[0].size == 8) {
if (value.ub[0] == 0x00 && value.ub[1] == 0x00 &&
value.ub[2] == 0x00 && value.ub[3] == 0xff) {
*clear_value = GFX11_DCC_CLEAR_0001_UNORM;
return true;
} else if (value.ub[0] == 0xff && value.ub[1] == 0xff &&
value.ub[2] == 0xff && value.ub[3] == 0x00) {
*clear_value = GFX11_DCC_CLEAR_1110_UNORM;
return true;
}
} else if (desc->nr_channels == 4 && desc->channel[0].size == 16) {
if (value.us[0] == 0x0000 && value.us[1] == 0x0000 &&
value.us[2] == 0x0000 && value.us[3] == 0xffff) {
*clear_value = GFX11_DCC_CLEAR_0001_UNORM;
return true;
} else if (value.us[0] == 0xffff && value.us[1] == 0xffff &&
value.us[2] == 0xffff && value.us[3] == 0x0000) {
*clear_value = GFX11_DCC_CLEAR_1110_UNORM;
return true;
}
if (desc->nr_channels == 2 && desc->channel[0].size == 8) {
if (value.ub[0] == 0x00 && value.ub[1] == 0xff) {
*clear_value = GFX11_DCC_CLEAR_0001_UNORM;
return true;
} else if (value.ub[0] == 0xff && value.ub[1] == 0x00) {
*clear_value = GFX11_DCC_CLEAR_1110_UNORM;
return true;
}
} else if (desc->nr_channels == 4 && desc->channel[0].size == 8) {
if (value.ub[0] == 0x00 && value.ub[1] == 0x00 &&
value.ub[2] == 0x00 && value.ub[3] == 0xff) {
*clear_value = GFX11_DCC_CLEAR_0001_UNORM;
return true;
} else if (value.ub[0] == 0xff && value.ub[1] == 0xff &&
value.ub[2] == 0xff && value.ub[3] == 0x00) {
*clear_value = GFX11_DCC_CLEAR_1110_UNORM;
return true;
}
} else if (desc->nr_channels == 4 && desc->channel[0].size == 16) {
if (value.us[0] == 0x0000 && value.us[1] == 0x0000 &&
value.us[2] == 0x0000 && value.us[3] == 0xffff) {
*clear_value = GFX11_DCC_CLEAR_0001_UNORM;
return true;
} else if (value.us[0] == 0xffff && value.us[1] == 0xffff &&
value.us[2] == 0xffff && value.us[3] == 0x0000) {
*clear_value = GFX11_DCC_CLEAR_1110_UNORM;
return true;
}
}

4
src/gallium/drivers/radeonsi/si_pipe.h
View File

@@ -178,9 +178,9 @@ enum si_clear_code
GFX11_DCC_CLEAR_1111_UNORM = DCC_CODE(0x02), /* all bits are 1 */
GFX11_DCC_CLEAR_1111_FP16 = DCC_CODE(0x04), /* all 16-bit words are 0x3c00, max 64bpp */
GFX11_DCC_CLEAR_1111_FP32 = DCC_CODE(0x06), /* all 32-bit words are 0x3f800000 */
/* Color bits are 0, alpha bits are 1; only 88, 8888, 16161616 with alpha_on_msb=1 */
/* Color bits are 0, alpha bits are 1; only 88, 8888, 16161616 */
GFX11_DCC_CLEAR_0001_UNORM = DCC_CODE(0x08),
/* Color bits are 1, alpha bits are 0, only 88, 8888, 16161616 with alpha_on_msb=1 */
/* Color bits are 1, alpha bits are 0, only 88, 8888, 16161616 */
GFX11_DCC_CLEAR_1110_UNORM = DCC_CODE(0x0A),
};