intel/fs: make use of load_ubo_uniform_block_intel
The principle is the same as the load_ssbo_uniform_block_intel. Whenever we see a uniform offset, load the data only once in GRFs to reduce register pressure. Iris shader-db run on DG2 : total instructions in shared programs: 23001325 -> 23094969 (0.41%) instructions in affected programs: 1775989 -> 1869633 (5.27%) helped: 764 HURT: 2097 helped stats (abs) min: 1 max: 102 x̄: 6.96 x̃: 2 helped stats (rel) min: 0.03% max: 16.91% x̄: 1.36% x̃: 0.63% HURT stats (abs) min: 1 max: 2461 x̄: 47.19 x̃: 7 HURT stats (rel) min: <.01% max: 199.34% x̄: 5.91% x̃: 2.60% 95% mean confidence interval for instructions value: 25.43 40.03 95% mean confidence interval for instructions %-change: 3.60% 4.33% Instructions are HURT. total loops in shared programs: 5847 -> 5847 (0.00%) loops in affected programs: 0 -> 0 helped: 0 HURT: 0 total cycles in shared programs: 839329852 -> 845491482 (0.73%) cycles in affected programs: 130229434 -> 136391064 (4.73%) helped: 1098 HURT: 2228 helped stats (abs) min: 1 max: 130102 x̄: 1340.64 x̃: 22 helped stats (rel) min: <.01% max: 64.25% x̄: 4.03% x̃: 0.71% HURT stats (abs) min: 1 max: 185309 x̄: 3426.24 x̃: 87 HURT stats (rel) min: <.01% max: 92.85% x̄: 8.12% x̃: 3.82% 95% mean confidence interval for cycles value: 1342.16 2362.97 95% mean confidence interval for cycles %-change: 3.70% 4.52% Cycles are HURT. total spills in shared programs: 10768 -> 11856 (10.10%) spills in affected programs: 9717 -> 10805 (11.20%) helped: 25 HURT: 28 total fills in shared programs: 13720 -> 16258 (18.50%) fills in affected programs: 12016 -> 14554 (21.12%) helped: 25 HURT: 28 total sends in shared programs: 1034790 -> 1031266 (-0.34%) sends in affected programs: 33416 -> 29892 (-10.55%) helped: 1005 HURT: 0 helped stats (abs) min: 1 max: 22 x̄: 3.51 x̃: 3 helped stats (rel) min: 1.69% max: 60.00% x̄: 15.20% x̃: 14.08% 95% mean confidence interval for sends value: -3.72 -3.29 95% mean confidence interval for sends %-change: -15.82% -14.57% Sends are helped. LOST: 26 GAINED: 183 shader-db on a number of VK/DX titles on DG2 : PERCENTAGE DELTAS Shaders Instrs Cycles age_of_wonders_III 1928 +0.02% -0.19% PERCENTAGE DELTAS Shaders Instrs Cycles Subgroup size Send messages Spill count Fill count Max live registers Max dispatch width assassins_creed_odyssey 2119 +1.12% -0.42% -0.03% -0.29% -9.10% -4.26% -0.64% +0.65% PERCENTAGE DELTAS Shaders Instrs Cycles Spill count Fill count Max live registers aztec_ruins_high 269 -0.05% -0.45% -0.29% -7.27% -0.33% PERCENTAGE DELTAS Shaders Instrs Cycles Max live registers Max dispatch width dark_souls_3_dxvk_g2 1420 +0.09% +0.24% +0.21% +0.12% (stats look bad, but it's just one shader affected) PERCENTAGE DELTAS Shaders Instrs Cycles Spill count Fill count Scratch Memory Size Max live registers fallout_4_dxvk_g2 1638 +0.67% +8.32% +16.02% +7.17% +100.00% +0.48% PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Spill count Fill count Max live registers Max dispatch width red_dead_redemption2 5969 +0.16% -0.04% -0.04% +0.01% +0.05% -0.20% +0.04% PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Max live registers Max dispatch width rise_of_the_tomb_raider_g2 12129 +2.19% +1.36% -1.23% -0.36% +2.04% PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Max live registers shooter-game 693 +0.07% -0.89% -0.09% -0.09% PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Max live registers Max dispatch width talos_g2 1140 +0.37% +3.80% -0.86% -0.67% +0.19% PERCENTAGE DELTAS Shaders Instrs Cycles Max live registers Max dispatch width total_war_warhammer2 477 +0.25% +0.66% -0.17% +0.10% PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Max live registers Max dispatch width witcher_3_dxvk_g2 1074 +0.75% -10.45% -0.15% -0.16% -0.16% PERCENTAGE DELTAS Shaders Instrs Cycles Send messages Max live registers wolfenstein_youngblood 1111 +0.52% +0.66% -0.59% -0.03% Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23477>
This commit is contained in:
Lionel Landwerlin
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Marge Bot
Marge Bot
parent
4a23a5a904
commit
5ae8a78d8c
@@ -4836,7 +4836,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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break;
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}
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case nir_intrinsic_load_ubo: {
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_ubo_uniform_block_intel: {
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fs_reg surface, surface_handle;
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if (get_nir_src_bindless(instr->src[0]))
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@@ -4845,16 +4846,72 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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surface = get_nir_buffer_intrinsic_index(bld, instr);
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if (!nir_src_is_const(instr->src[1])) {
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fs_reg base_offset = retype(get_nir_src(instr->src[1]),
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BRW_REGISTER_TYPE_UD);
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if (instr->intrinsic == nir_intrinsic_load_ubo) {
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/* load_ubo with non-uniform offset */
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fs_reg base_offset = retype(get_nir_src(instr->src[1]),
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BRW_REGISTER_TYPE_UD);
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for (int i = 0; i < instr->num_components; i++)
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VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i),
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surface, surface_handle,
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base_offset, i * type_sz(dest.type),
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nir_dest_bit_size(instr->dest) / 8);
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for (int i = 0; i < instr->num_components; i++)
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VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i),
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surface, surface_handle,
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base_offset, i * type_sz(dest.type),
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nir_dest_bit_size(instr->dest) / 8);
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prog_data->has_ubo_pull = true;
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prog_data->has_ubo_pull = true;
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} else {
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/* load_ubo with uniform offset */
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const fs_builder ubld1 = bld.exec_all().group(1, 0);
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const fs_builder ubld8 = bld.exec_all().group(8, 0);
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const fs_builder ubld16 = bld.exec_all().group(16, 0);
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fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
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srcs[SURFACE_LOGICAL_SRC_SURFACE] = surface;
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srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = surface_handle;
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const nir_src load_offset = instr->src[1];
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if (nir_src_is_const(load_offset)) {
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fs_reg addr = ubld8.vgrf(BRW_REGISTER_TYPE_UD);
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ubld8.MOV(addr, brw_imm_ud(nir_src_as_uint(load_offset)));
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] = component(addr, 0);
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} else {
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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bld.emit_uniformize(get_nir_src(load_offset));
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}
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const unsigned total_dwords = ALIGN(instr->num_components, REG_SIZE / 4);
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unsigned loaded_dwords = 0;
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const fs_reg packed_consts =
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ubld1.vgrf(BRW_REGISTER_TYPE_UD, total_dwords);
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while (loaded_dwords < total_dwords) {
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const unsigned block =
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choose_oword_block_size_dwords(devinfo,
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total_dwords - loaded_dwords);
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const unsigned block_bytes = block * 4;
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(block);
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const fs_builder &ubld = block <= 8 ? ubld8 : ubld16;
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ubld.emit(SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL,
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retype(byte_offset(packed_consts, loaded_dwords * 4), BRW_REGISTER_TYPE_UD),
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srcs, SURFACE_LOGICAL_NUM_SRCS)->size_written = align(block_bytes, REG_SIZE);
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loaded_dwords += block;
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ubld1.ADD(srcs[SURFACE_LOGICAL_SRC_ADDRESS],
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srcs[SURFACE_LOGICAL_SRC_ADDRESS],
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brw_imm_ud(block_bytes));
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}
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for (unsigned c = 0; c < instr->num_components; c++) {
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bld.MOV(retype(offset(dest, bld, c), BRW_REGISTER_TYPE_UD),
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component(packed_consts, c));
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}
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prog_data->has_ubo_pull = true;
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}
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} else {
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/* Even if we are loading doubles, a pull constant load will load
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* a 32-bit vec4, so should only reserve vgrf space for that. If we
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@@ -1308,6 +1308,7 @@ brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
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return false;
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if (low->intrinsic == nir_intrinsic_load_global_const_block_intel ||
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low->intrinsic == nir_intrinsic_load_ubo_uniform_block_intel ||
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low->intrinsic == nir_intrinsic_load_ssbo_uniform_block_intel ||
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low->intrinsic == nir_intrinsic_load_shared_uniform_block_intel) {
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if (num_components > 4) {
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@@ -37,6 +37,7 @@ brw_nir_blockify_uniform_loads_instr(nir_builder *b,
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_ssbo:
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/* BDW PRMs, Volume 7: 3D-Media-GPGPU: OWord Block ReadWrite:
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*
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@@ -60,7 +61,10 @@ brw_nir_blockify_uniform_loads_instr(nir_builder *b,
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if (!devinfo->has_lsc && nir_dest_num_components(intrin->dest) < 4)
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return false;
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intrin->intrinsic = nir_intrinsic_load_ssbo_uniform_block_intel;
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intrin->intrinsic =
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intrin->intrinsic == nir_intrinsic_load_ubo ?
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nir_intrinsic_load_ubo_uniform_block_intel :
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nir_intrinsic_load_ssbo_uniform_block_intel;
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return true;
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case nir_intrinsic_load_shared:
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@@ -92,6 +92,7 @@ brw_nir_lower_non_uniform_intrinsic(nir_builder *b,
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case nir_intrinsic_ssbo_atomic_swap:
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case nir_intrinsic_load_ssbo_block_intel:
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case nir_intrinsic_store_ssbo_block_intel:
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case nir_intrinsic_load_ubo_uniform_block_intel:
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case nir_intrinsic_load_ssbo_uniform_block_intel:
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case nir_intrinsic_image_load_raw_intel:
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case nir_intrinsic_image_store_raw_intel:
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