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broadcom/vc5: Add compiler support for V3D 4.x texturing.

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This commit is contained in:
Eric Anholt
2018-01-10 12:51:08 -08:00
parent 028f6b327c
commit 5aaea3c4a0
7 changed files with 283 additions and 6 deletions
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1
src/broadcom/Makefile.sources
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@@ -31,6 +31,7 @@ BROADCOM_FILES = \
compiler/qpu_validate.c \
compiler/v3d33_tex.c \
compiler/v3d33_vpm_setup.c \
compiler/v3d40_tex.c \
compiler/v3d_compiler.h \
compiler/v3d_nir_lower_io.c \
compiler/v3d_nir_lower_txf_ms.c \

1
src/broadcom/compiler/meson.build
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@@ -31,6 +31,7 @@ libbroadcom_compiler_files = files(
'qpu_schedule.c',
'qpu_validate.c',
'v3d33_tex.c',
'v3d40_tex.c',
'v3d33_vpm_setup.c',
'v3d_compiler.h',
'v3d_nir_lower_io.c',

3
src/broadcom/compiler/nir_to_vir.c
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@@ -334,6 +334,9 @@ ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
break;
}
if (c->devinfo->ver >= 40)
v3d40_vir_emit_tex(c, instr);
else
v3d33_vir_emit_tex(c, instr);
}

15
src/broadcom/compiler/qpu_schedule.c
View File

@@ -84,6 +84,7 @@ struct schedule_state {
struct schedule_node *last_sf;
struct schedule_node *last_vpm_read;
struct schedule_node *last_tmu_write;
struct schedule_node *last_tmu_config;
struct schedule_node *last_tlb;
struct schedule_node *last_vpm;
struct schedule_node *last_unif;
@@ -195,6 +196,16 @@ process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
add_write_dep(state, &state->last_rf[waddr], n);
} else if (v3d_qpu_magic_waddr_is_tmu(waddr)) {
add_write_dep(state, &state->last_tmu_write, n);
switch (waddr) {
case V3D_QPU_WADDR_TMUS:
case V3D_QPU_WADDR_TMUSCM:
case V3D_QPU_WADDR_TMUSF:
case V3D_QPU_WADDR_TMUSLOD:
add_write_dep(state, &state->last_tmu_config, n);
break;
default:
break;
}
} else if (v3d_qpu_magic_waddr_is_sfu(waddr)) {
/* Handled by v3d_qpu_writes_r4() check. */
} else {
@@ -388,6 +399,7 @@ calculate_deps(struct schedule_state *state, struct schedule_node *n)
add_write_dep(state, &state->last_tlb, n);
add_write_dep(state, &state->last_tmu_write, n);
add_write_dep(state, &state->last_tmu_config, n);
}
if (inst->sig.ldtmu) {
@@ -396,6 +408,9 @@ calculate_deps(struct schedule_state *state, struct schedule_node *n)
add_write_dep(state, &state->last_tmu_write, n);
}
if (inst->sig.wrtmuc)
add_write_dep(state, &state->last_tmu_config, n);
if (inst->sig.ldtlb | inst->sig.ldtlbu)
add_read_dep(state, state->last_tlb, n);

237
src/broadcom/compiler/v3d40_tex.c Normal file
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@@ -0,0 +1,237 @@
/*
* Copyright © 2016-2018 Broadcom
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "v3d_compiler.h"
/* We don't do any address packing. */
#define __gen_user_data void
#define __gen_address_type uint32_t
#define __gen_address_offset(reloc) (*reloc)
#define __gen_emit_reloc(cl, reloc)
#include "cle/v3d_packet_v41_pack.h"
static void
vir_TMU_WRITE(struct v3d_compile *c, enum v3d_qpu_waddr waddr, struct qreg val)
{
vir_MOV_dest(c, vir_reg(QFILE_MAGIC, waddr), val);
}
static void
vir_WRTMUC(struct v3d_compile *c, enum quniform_contents contents, uint32_t data)
{
struct qinst *inst = vir_NOP(c);
inst->qpu.sig.wrtmuc = true;
inst->has_implicit_uniform = true;
inst->src[0] = vir_uniform(c, contents, data);
}
void
v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
{
unsigned unit = instr->texture_index;
struct V3D41_TMU_CONFIG_PARAMETER_0 p0_unpacked = {
};
struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked = {
.output_type_32_bit = (c->key->tex[unit].return_size == 32 &&
!instr->is_shadow),
.unnormalized_coordinates = (instr->sampler_dim ==
GLSL_SAMPLER_DIM_RECT),
};
struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked = {
.op = V3D_TMU_OP_REGULAR,
.gather_mode = instr->op == nir_texop_tg4,
.gather_component = instr->component,
.coefficient_mode = instr->op == nir_texop_txd,
};
int non_array_components = instr->coord_components - instr->is_array;
struct qreg s;
for (unsigned i = 0; i < instr->num_srcs; i++) {
switch (instr->src[i].src_type) {
case nir_tex_src_coord:
/* S triggers the lookup, so save it for the end. */
s = ntq_get_src(c, instr->src[i].src, 0);
if (non_array_components > 1) {
vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUT,
ntq_get_src(c, instr->src[i].src,
1));
}
if (non_array_components > 2) {
vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUR,
ntq_get_src(c, instr->src[i].src,
2));
}
if (instr->is_array) {
vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUI,
ntq_get_src(c, instr->src[i].src,
instr->coord_components - 1));
}
break;
case nir_tex_src_bias:
vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUB,
ntq_get_src(c, instr->src[i].src, 0));
break;
case nir_tex_src_lod:
vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUB,
ntq_get_src(c, instr->src[i].src, 0));
if (instr->op != nir_texop_txf &&
instr->op != nir_texop_tg4) {
p2_unpacked.disable_autolod = true;
}
break;
case nir_tex_src_comparator:
vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUDREF,
ntq_get_src(c, instr->src[i].src, 0));
break;
case nir_tex_src_offset: {
nir_const_value *offset =
nir_src_as_const_value(instr->src[i].src);
p2_unpacked.offset_s = offset->i32[0];
if (instr->coord_components >= 2)
p2_unpacked.offset_t = offset->i32[1];
if (instr->coord_components >= 3)
p2_unpacked.offset_r = offset->i32[2];
break;
}
default:
unreachable("unknown texture source");
}
}
/* Limit the number of channels returned to both how many the NIR
* instruction writes and how many the instruction could produce.
*/
uint32_t instr_return_channels = nir_tex_instr_dest_size(instr);
if (!p1_unpacked.output_type_32_bit)
instr_return_channels = (instr_return_channels + 1) / 2;
p0_unpacked.return_words_of_texture_data =
(1 << MIN2(instr_return_channels,
c->key->tex[unit].return_channels)) - 1;
uint32_t p0_packed;
V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL,
(uint8_t *)&p0_packed,
&p0_unpacked);
uint32_t p1_packed;
V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL,
(uint8_t *)&p1_packed,
&p1_unpacked);
uint32_t p2_packed;
V3D41_TMU_CONFIG_PARAMETER_2_pack(NULL,
(uint8_t *)&p2_packed,
&p2_unpacked);
/* Load unit number into the high bits of the texture or sampler
* address field, which will be be used by the driver to decide which
* texture to put in the actual address field.
*/
p0_packed |= unit << 24;
p1_packed |= unit << 24;
vir_WRTMUC(c, QUNIFORM_TMU_CONFIG_P0, p0_packed);
vir_WRTMUC(c, QUNIFORM_TMU_CONFIG_P1, p1_packed);
vir_WRTMUC(c, QUNIFORM_CONSTANT, p2_packed);
if (instr->op == nir_texop_txf) {
assert(instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE);
vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSF, s);
} else if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSCM, s);
} else {
vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUS, s);
}
vir_emit_thrsw(c);
struct qreg return_values[4];
for (int i = 0; i < 4; i++) {
/* Swizzling .zw of an RG texture should give undefined
* results, not crash the compiler.
*/
if (p0_unpacked.return_words_of_texture_data & (1 << i))
return_values[i] = vir_LDTMU(c);
else
return_values[i] = c->undef;
}
for (int i = 0; i < nir_tex_instr_dest_size(instr); i++) {
struct qreg chan;
if (!p1_unpacked.output_type_32_bit) {
STATIC_ASSERT(PIPE_SWIZZLE_X == 0);
chan = return_values[i / 2];
if (nir_alu_type_get_base_type(instr->dest_type) ==
nir_type_float) {
enum v3d_qpu_input_unpack unpack;
if (i & 1)
unpack = V3D_QPU_UNPACK_H;
else
unpack = V3D_QPU_UNPACK_L;
chan = vir_FMOV(c, chan);
vir_set_unpack(c->defs[chan.index], 0, unpack);
} else {
/* If we're unpacking the low field, shift it
* up to the top first.
*/
if ((i & 1) == 0) {
chan = vir_SHL(c, chan,
vir_uniform_ui(c, 16));
}
/* Do proper sign extension to a 32-bit int. */
if (nir_alu_type_get_base_type(instr->dest_type) ==
nir_type_int) {
chan = vir_ASR(c, chan,
vir_uniform_ui(c, 16));
} else {
chan = vir_SHR(c, chan,
vir_uniform_ui(c, 16));
}
}
} else {
chan = vir_MOV(c, return_values[i]);
}
ntq_store_dest(c, &instr->dest, i, chan);
}
}

21
src/broadcom/compiler/v3d_compiler.h
View File

@@ -33,6 +33,7 @@
#include "util/macros.h"
#include "common/v3d_debug.h"
#include "common/v3d_device_info.h"
#include "compiler/nir/nir.h"
#include "util/list.h"
#include "util/u_math.h"
@@ -172,7 +173,7 @@ enum quniform_contents {
QUNIFORM_USER_CLIP_PLANE,
/**
* A reference to a texture config parameter 0 uniform.
* A reference to a V3D 3.x texture config parameter 0 uniform.
*
* This is a uniform implicitly loaded with a QPU_W_TMU* write, which
* defines texture type, miplevels, and such. It will be found as a
@@ -213,7 +214,7 @@ enum quniform_contents {
QUNIFORM_TEXTURE_CONFIG_P0_32,
/**
* A reference to a texture config parameter 1 uniform.
* A reference to a V3D 3.x texture config parameter 1 uniform.
*
* This is a uniform implicitly loaded with a QPU_W_TMU* write, which
* has the pointer to the indirect texture state. Our data[] field
@@ -222,6 +223,13 @@ enum quniform_contents {
*/
QUNIFORM_TEXTURE_CONFIG_P1,
/* A a V3D 4.x texture config parameter. The high 8 bits will be
* which texture or sampler is being sampled, and the driver must
* replace the address field with the appropriate address.
*/
QUNIFORM_TMU_CONFIG_P0,
QUNIFORM_TMU_CONFIG_P1,
QUNIFORM_TEXTURE_FIRST_LEVEL,
QUNIFORM_TEXTURE_WIDTH,
@@ -691,6 +699,7 @@ void vir_lower_uniforms(struct v3d_compile *c);
void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
@@ -896,8 +905,16 @@ vir_NOP(struct v3d_compile *c)
static inline struct qreg
vir_LDTMU(struct v3d_compile *c)
{
if (c->devinfo->ver >= 41) {
struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
c->undef, c->undef);
ldtmu->qpu.sig.ldtmu = true;
return vir_emit_def(c, ldtmu);
} else {
vir_NOP(c)->qpu.sig.ldtmu = true;
return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
}
}
/*

5
src/broadcom/compiler/vir.c
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@@ -109,8 +109,11 @@ vir_has_side_effects(struct v3d_compile *c, struct qinst *inst)
}
}
if (inst->qpu.sig.ldtmu || inst->qpu.sig.thrsw)
if (inst->qpu.sig.ldtmu ||
inst->qpu.sig.wrtmuc ||
inst->qpu.sig.thrsw) {
return true;
}
return false;
}