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radv/gfx11: re-enable 0001/1110 clear values

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Since 87444bb7ab, vi_alpha_is_on_msb always
returned false here. The new version matches radeonsi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
This commit is contained in:
Rhys Perry
2023-07-31 12:30:41 +01:00
committed by Marge Bot
parent 19f73f8eb4
commit 5a7efccdc3
1 changed files with 23 additions and 25 deletions
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48
src/amd/vulkan/meta/radv_meta_clear.c
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@@ -1565,31 +1565,29 @@ gfx11_get_fast_clear_parameters(struct radv_device *device, const struct radv_im
return true;
}
if (vi_alpha_is_on_msb(device, iview->vk.format)) {
if (desc->nr_channels == 2 && desc->channel[0].size == 8) {
if (value.ub[0] == 0x00 && value.ub[1] == 0xff) {
*reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM;
return true;
} else if (value.ub[0] == 0xff && value.ub[1] == 0x00) {
*reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM;
return true;
}
} else if (desc->nr_channels == 4 && desc->channel[0].size == 8) {
if (value.ub[0] == 0x00 && value.ub[1] == 0x00 && value.ub[2] == 0x00 && value.ub[3] == 0xff) {
*reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM;
return true;
} else if (value.ub[0] == 0xff && value.ub[1] == 0xff && value.ub[2] == 0xff && value.ub[3] == 0x00) {
*reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM;
return true;
}
} else if (desc->nr_channels == 4 && desc->channel[0].size == 16) {
if (value.us[0] == 0x0000 && value.us[1] == 0x0000 && value.us[2] == 0x0000 && value.us[3] == 0xffff) {
*reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM;
return true;
} else if (value.us[0] == 0xffff && value.us[1] == 0xffff && value.us[2] == 0xffff && value.us[3] == 0x0000) {
*reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM;
return true;
}
if (desc->nr_channels == 2 && desc->channel[0].size == 8) {
if (value.ub[0] == 0x00 && value.ub[1] == 0xff) {
*reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM;
return true;
} else if (value.ub[0] == 0xff && value.ub[1] == 0x00) {
*reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM;
return true;
}
} else if (desc->nr_channels == 4 && desc->channel[0].size == 8) {
if (value.ub[0] == 0x00 && value.ub[1] == 0x00 && value.ub[2] == 0x00 && value.ub[3] == 0xff) {
*reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM;
return true;
} else if (value.ub[0] == 0xff && value.ub[1] == 0xff && value.ub[2] == 0xff && value.ub[3] == 0x00) {
*reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM;
return true;
}
} else if (desc->nr_channels == 4 && desc->channel[0].size == 16) {
if (value.us[0] == 0x0000 && value.us[1] == 0x0000 && value.us[2] == 0x0000 && value.us[3] == 0xffff) {
*reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM;
return true;
} else if (value.us[0] == 0xffff && value.us[1] == 0xffff && value.us[2] == 0xffff && value.us[3] == 0x0000) {
*reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM;
return true;
}
}