ac: add tables for CP register shadowing

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

src/amd/Makefile.sources

@@ -49,7 +49,9 @@ AMD_COMMON_FILES = \
 	common/ac_shader_args.c \
 	common/ac_shader_args.h \
 	common/ac_shader_util.c \
-	common/ac_shader_util.h
+	common/ac_shader_util.h \
+	common/ac_shadowed_regs.c \
+	common/ac_shadowed_regs.h
 
 AMD_COMMON_LLVM_FILES = \
 	llvm/ac_llvm_build.c \

src/amd/common/ac_shadowed_regs.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright © 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+
+#ifndef AC_SHADOWED_REGS
+#define AC_SHADOWED_REGS
+
+#include "ac_gpu_info.h"
+
+struct radeon_cmdbuf;
+
+struct ac_reg_range {
+   unsigned offset;
+   unsigned size;
+};
+
+enum ac_reg_range_type {
+   SI_REG_RANGE_UCONFIG,
+   SI_REG_RANGE_CONTEXT,
+   SI_REG_RANGE_SH,
+   SI_REG_RANGE_CS_SH,
+   SI_NUM_SHADOWED_REG_RANGES,
+
+   SI_REG_RANGE_NON_SHADOWED = SI_NUM_SHADOWED_REG_RANGES,
+   SI_NUM_ALL_REG_RANGES,
+};
+
+typedef void (*set_context_reg_seq_array_fn)(struct radeon_cmdbuf *cs, unsigned reg,
+                                             unsigned num, const uint32_t *values);
+
+void ac_get_reg_ranges(enum chip_class chip_class, enum radeon_family family,
+                       enum ac_reg_range_type type, unsigned *num_ranges,
+                       const struct ac_reg_range **ranges);
+void ac_emulate_clear_state(const struct radeon_info *info,
+                            struct radeon_cmdbuf *cs,
+                            set_context_reg_seq_array_fn set_context_reg_seq_array);
+
+#endif

src/amd/common/meson.build

@@ -64,6 +64,8 @@ amd_common_files = files(
   'ac_surface.h',
   'ac_debug.c',
   'ac_debug.h',
+  'ac_shadowed_regs.c',
+  'ac_shadowed_regs.h',
 )
 
 libamd_common = static_library(

src/amd/common/sid.h

@@ -35,7 +35,20 @@
 #define SI_CONTEXT_REG_END                   0x00030000
 #define CIK_UCONFIG_REG_OFFSET               0x00030000
 #define CIK_UCONFIG_REG_END                  0x00040000
+#define SI_UCONFIG_PERF_REG_OFFSET           0x00034000
+#define SI_UCONFIG_PERF_REG_END              0x00038000
 
+/* For register shadowing: */
+#define SI_SH_REG_SPACE_SIZE			(SI_SH_REG_END - SI_SH_REG_OFFSET)
+#define SI_CONTEXT_REG_SPACE_SIZE		(SI_CONTEXT_REG_END - SI_CONTEXT_REG_OFFSET)
+#define SI_UCONFIG_REG_SPACE_SIZE		(CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET)
+#define SI_UCONFIG_PERF_REG_SPACE_SIZE          (SI_UCONFIG_PERF_REG_END - SI_UCONFIG_PERF_REG_OFFSET)
+
+#define SI_SHADOWED_SH_REG_OFFSET		0
+#define SI_SHADOWED_CONTEXT_REG_OFFSET		SI_SH_REG_SPACE_SIZE
+#define SI_SHADOWED_UCONFIG_REG_OFFSET		(SI_SH_REG_SPACE_SIZE + SI_CONTEXT_REG_SPACE_SIZE)
+#define SI_SHADOWED_REG_BUFFER_SIZE		(SI_SH_REG_SPACE_SIZE + SI_CONTEXT_REG_SPACE_SIZE + \
+						 SI_UCONFIG_REG_SPACE_SIZE)
 
 #define EVENT_TYPE_CACHE_FLUSH                  0x6
 #define EVENT_TYPE_PS_PARTIAL_FLUSH            0x10

src/amd/registers/gfx10.json

@@ -6425,6 +6425,16 @@
    "name": "SQ_THREAD_TRACE_DROPPED_CNTR",
    "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
   },
+  {
+   "chips": ["gfx10"],
+   "map": {"at": 36152, "to": "mm"},
+   "name": "SQ_THREAD_TRACE_HP3D_MARKER_CNTR"
+  },
+  {
+   "chips": ["gfx10"],
+   "map": {"at": 36156, "to": "mm"},
+   "name": "SQ_THREAD_TRACE_STATUS2_GFX103"
+  },
   {
    "chips": ["gfx10"],
    "map": {"at": 37804, "to": "mm"},