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pvr: Use alignas instead of ALIGN_ATTR and remove ALIGN_ATTR

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Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23982>
This commit is contained in:
Yonggang Luo
2023-07-04 12:35:21 +08:00
committed by Marge Bot
parent dadb7244bb
commit 59e2760d8f
3 changed files with 36 additions and 34 deletions
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41
src/imagination/vulkan/winsys/pvrsrvkm/fw-api/pvr_rogue_fwif.h
View File

@@ -31,6 +31,7 @@
#include "hwdef/rogue_hw_defs.h"
#include "pvr_rogue_fwif_shared.h"
#include "pvr_winsys.h"
#include "util/macros.h"
/**
* \name Frag DM command flags.
@@ -208,8 +209,8 @@ struct rogue_fwif_cmd_ta {
*/
struct rogue_fwif_cmd_ta_3d_shared cmd_shared;
struct rogue_fwif_ta_regs ALIGN_ATTR(8) regs;
uint32_t ALIGN_ATTR(8) flags;
alignas(8) struct rogue_fwif_ta_regs regs;
alignas(8) uint32_t flags;
/**
* Holds the TA/3D fence value to allow the 3D partial render command
* to go through.
@@ -217,8 +218,8 @@ struct rogue_fwif_cmd_ta {
struct rogue_fwif_ufo partial_render_ta_3d_fence;
/* Only used when BRN 44455 or BRN 63027 present. */
struct rogue_fwif_dummy_rgnhdr_init_geom_regs
ALIGN_ATTR(8) dummy_rgnhdr_init_geom_regs;
alignas(8) struct rogue_fwif_dummy_rgnhdr_init_geom_regs
dummy_rgnhdr_init_geom_regs;
/* Only used when BRN 61484 or BRN 66333 present. */
uint32_t brn61484_66333_live_rt;
@@ -241,7 +242,7 @@ static_assert(
struct rogue_fwif_3d_regs {
/**
* All 32 bit values should be added in the top section. This then requires
* only a single ALIGN_ATTR(8) to align all the 64 bit values in the second
* only a single alignas(8) to align all the 64 bit values in the second
* section.
*/
uint32_t usc_pixel_output_ctrl;
@@ -280,8 +281,8 @@ struct rogue_fwif_3d_regs {
/* Only used when feature ISP_ZLS_D24_S8_PACKING_OGL_MODE present. */
uint32_t rgx_cr_blackpearl_fix;
/* All values below the ALIGN_ATTR(8) must be 64 bit. */
uint64_t ALIGN_ATTR(8) isp_scissor_base;
/* All values below the alignas(8) must be 64 bit. */
alignas(8) uint64_t isp_scissor_base;
uint64_t isp_dbias_base;
uint64_t isp_oclqry_base;
uint64_t isp_zlsctl;
@@ -330,9 +331,9 @@ struct rogue_fwif_cmd_3d {
* This region must be the first member so Kernel can easily access it.
* For more info, see rogue_fwif_cmd_ta_3d_shared definition.
*/
struct rogue_fwif_cmd_ta_3d_shared ALIGN_ATTR(8) cmd_shared;
alignas(8) struct rogue_fwif_cmd_ta_3d_shared cmd_shared;
struct rogue_fwif_3d_regs ALIGN_ATTR(8) regs;
alignas(8) struct rogue_fwif_3d_regs regs;
/** command control flags. */
uint32_t flags;
/** Stride IN BYTES for Z-Buffer in case of RTAs. */
@@ -357,7 +358,7 @@ static_assert(
struct rogue_fwif_transfer_regs {
/**
* All 32 bit values should be added in the top section. This then requires
* only a single ALIGN_ATTR(8) to align all the 8 byte values in the second
* only a single alignas(8) to align all the 8 byte values in the second
* section.
*/
uint32_t isp_bgobjvals;
@@ -387,8 +388,8 @@ struct rogue_fwif_transfer_regs {
/* Only used when feature GPU_MULTICORE_SUPPORT present. */
uint32_t frag_screen;
/** All values below the ALIGN_ATTR must be 64 bit. */
uint64_t ALIGN_ATTR(8) pds_bgnd0_base;
/** All values below the alignas(8) must be 64 bit. */
alignas(8) uint64_t pds_bgnd0_base;
uint64_t pds_bgnd1_base;
uint64_t pds_bgnd3_sizeinfo;
@@ -404,8 +405,8 @@ struct rogue_fwif_transfer_regs {
* ROGUE_FWIF_CCB_CMD_TYPE_TQ_3D type client CCB command.
*/
struct rogue_fwif_cmd_transfer {
struct rogue_fwif_cmd_common ALIGN_ATTR(8) cmn;
struct rogue_fwif_transfer_regs ALIGN_ATTR(8) regs;
alignas(8) struct rogue_fwif_cmd_common cmn;
alignas(8) struct rogue_fwif_transfer_regs regs;
uint32_t flags;
@@ -431,8 +432,8 @@ struct rogue_fwif_2d_regs {
};
struct rogue_fwif_cmd_2d {
struct rogue_fwif_cmd_common ALIGN_ATTR(8) cmn;
struct rogue_fwif_2d_regs ALIGN_ATTR(8) regs;
alignas(8) struct rogue_fwif_cmd_common cmn;
alignas(8) struct rogue_fwif_2d_regs regs;
uint32_t flags;
};
@@ -447,7 +448,7 @@ static_assert(
/** Command to handle aborts. */
struct rogue_fwif_cmd_abort {
struct rogue_fwif_cmd_ta_3d_shared ALIGN_ATTR(8) cmd_shared;
alignas(8) struct rogue_fwif_cmd_ta_3d_shared cmd_shared;
};
/***********************************************
@@ -498,9 +499,9 @@ struct rogue_fwif_cdm_regs {
* Rouge Compute command.
*/
struct rogue_fwif_cmd_compute {
struct rogue_fwif_cmd_common ALIGN_ATTR(8) cmn;
struct rogue_fwif_cdm_regs ALIGN_ATTR(8) regs;
uint32_t ALIGN_ATTR(8) flags;
alignas(8) struct rogue_fwif_cmd_common cmn;
alignas(8) struct rogue_fwif_cdm_regs regs;
alignas(8) uint32_t flags;
/* Only used when feature UNIFIED_STORE_VIRTUAL_PARTITIONING present. */
uint32_t num_temp_regions;

3
src/imagination/vulkan/winsys/pvrsrvkm/fw-api/pvr_rogue_fwif_rf.h
View File

@@ -27,6 +27,7 @@
#include <stdint.h>
#include "pvr_rogue_fwif_shared.h"
#include "util/macros.h"
struct rogue_fwif_rf_regs {
union {
@@ -40,7 +41,7 @@ struct rogue_fwif_rf_regs {
struct rogue_fwif_rf_cmd {
/* THIS MUST BE THE LAST MEMBER OF THE CONTAINING STRUCTURE */
struct rogue_fwif_rf_regs ALIGN_ATTR(8) regs;
alignas(8) struct rogue_fwif_rf_regs regs;
};
#endif /* PVR_ROGUE_FWIF_RF_H */

26
src/imagination/vulkan/winsys/pvrsrvkm/fw-api/pvr_rogue_fwif_shared.h
View File

@@ -27,7 +27,7 @@
#include <stdbool.h>
#include <stdint.h>
#define ALIGN_ATTR(x) __attribute__((aligned(x)))
#include "util/macros.h"
/** Indicates the number of RTDATAs per RTDATASET. */
#define ROGUE_FWIF_NUM_RTDATAS 2U
@@ -63,10 +63,10 @@ struct rogue_fwif_dev_addr {
};
struct rogue_fwif_dma_addr {
uint64_t ALIGN_ATTR(8) dev_vaddr;
alignas(8) uint64_t dev_vaddr;
struct rogue_fwif_dev_addr fw_addr;
uint32_t padding;
} ALIGN_ATTR(8);
};
/**
* \brief Command data for fence & update types Client CCB commands.
@@ -80,11 +80,11 @@ struct rogue_fwif_ufo {
struct rogue_fwif_cleanup_ctl {
/** Number of commands received by the FW. */
uint32_t submitted_cmds;
alignas(8) uint32_t submitted_cmds;
/** Number of commands executed by the FW. */
uint32_t executed_cmds;
} ALIGN_ATTR(8);
};
#define ROGUE_FWIF_PRBUFFER_START 0U
#define ROGUE_FWIF_PRBUFFER_ZSBUFFER 0U
@@ -103,16 +103,16 @@ enum rogue_fwif_prbuffer_state {
*/
struct rogue_fwif_prbuffer {
/** Buffer ID. */
uint32_t buffer_id;
alignas(8) uint32_t buffer_id;
/** Needs on-demand Z/S/MSAA buffer allocation. */
bool ALIGN_ATTR(4) on_demand;
alignas(4) bool on_demand;
/** Z/S/MSAA - Buffer state. */
enum rogue_fwif_prbuffer_state state;
/** Cleanup state. */
struct rogue_fwif_cleanup_ctl cleanup_state;
/** Compatibility and other flags. */
uint32_t pr_buffer_flags;
} ALIGN_ATTR(8);
};
/**
* Used to share frame numbers across UM-KM-FW,
@@ -167,7 +167,7 @@ struct rogue_fwif_cmd_ta_3d_shared {
*/
struct rogue_fwif_cccb_ctl {
/** Host write offset into CCB. This must be aligned to 16 bytes. */
uint32_t write_offset;
alignas(8) uint32_t write_offset;
/**
* Firmware read offset into CCB. Points to the command that is runnable
@@ -193,7 +193,7 @@ struct rogue_fwif_cccb_ctl {
uint32_t read_offset4;
uint32_t padding;
} ALIGN_ATTR(8);
};
#define ROGUE_FW_LOCAL_FREELIST 0U
#define ROGUE_FW_GLOBAL_FREELIST 1U
@@ -254,8 +254,8 @@ struct rogue_fwif_cdm_regs_cswitch {
*/
struct rogue_fwif_static_rendercontext_state {
/** Geom registers for ctx switch. */
struct rogue_fwif_ta_regs_cswitch
ALIGN_ATTR(8) ctx_switch_geom_regs[ROGUE_NUM_GEOM_CORES_SIZE];
alignas(8) struct rogue_fwif_ta_regs_cswitch
ctx_switch_geom_regs[ROGUE_NUM_GEOM_CORES_SIZE];
};
#define ROGUE_FWIF_STATIC_RENDERCONTEXT_SIZE \
@@ -263,7 +263,7 @@ struct rogue_fwif_static_rendercontext_state {
struct rogue_fwif_static_computecontext_state {
/** CDM registers for ctx switch. */
struct rogue_fwif_cdm_regs_cswitch ALIGN_ATTR(8) ctx_switch_regs;
alignas(8) struct rogue_fwif_cdm_regs_cswitch ctx_switch_regs;
};
#define ROGUE_FWIF_STATIC_COMPUTECONTEXT_SIZE \