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i965: Disallow linear blits that are not cacheline aligned.

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The BLT engine on Gen8+ requires linear surfaces to be cacheline
aligned.  This restriction was added as part of converting the BLT to
use 48-bit addressing.

The main user, intel_emit_linear_blit, now handles this properly.
But we might also have linear miptrees; just refuse to blit those.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
This commit is contained in:
Kenneth Graunke
2015-04-21 12:32:38 -07:00
parent 8c17d53823
commit 5957da1edb
1 changed files with 19 additions and 8 deletions
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27
src/mesa/drivers/dri/i965/intel_blit.c
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@@ -271,6 +271,20 @@ intel_miptree_blit(struct brw_context *brw,
return true;
}
static bool
alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling)
{
/* Tiled buffers must be page-aligned (4K). */
if (tiling != I915_TILING_NONE)
return (offset & 4095) == 0;
/* On Gen8+, linear buffers must be cacheline-aligned. */
if (brw->gen >= 8)
return (offset & 63) == 0;
return true;
}
/* Copy BitBlt
*/
bool
@@ -296,14 +310,11 @@ intelEmitCopyBlit(struct brw_context *brw,
bool dst_y_tiled = dst_tiling == I915_TILING_Y;
bool src_y_tiled = src_tiling == I915_TILING_Y;
if (dst_tiling != I915_TILING_NONE) {
if (dst_offset & 4095)
return false;
}
if (src_tiling != I915_TILING_NONE) {
if (src_offset & 4095)
return false;
}
if (!alignment_valid(brw, dst_offset, dst_tiling))
return false;
if (!alignment_valid(brw, src_offset, src_tiling))
return false;
if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
return false;